From patchwork Fri Oct 19 01:08:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 149197 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp2681183lji; Thu, 18 Oct 2018 18:11:02 -0700 (PDT) X-Google-Smtp-Source: ACcGV63b0XZ+S29/zSWqSmflC8sIgbRQMW0+wu51D3mgyL88+6wS/d50QY8fapxIKOADypIw5cM9 X-Received: by 2002:a62:1551:: with SMTP id 78-v6mr32391999pfv.178.1539911462369; Thu, 18 Oct 2018 18:11:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539911462; cv=none; d=google.com; s=arc-20160816; b=P3GvZVECWb02PTqh5MDp/3bOZSQYgrY+objezBqy8m2Qwy9zIO0y/t9IN4pTgSFcLQ qEpVl/2p7QvwbRq5Avb0T9Z21iaLg6xtY/+hSFdvXkFw+GNIUGJhVtnJqmlgCamie7eg kSdZrSbNiMpj0yOnJV9IU+ugaeDPY1ui0o5EYqkIyu/FGoCsogbu0EbJuSXqiwouzc9t uRDNTyNNiUov+xO5hw1/vy2jdiryHxdVvg7NU6Cf08kWvCiWIexPJplIPs2u9WemSt0m 51AP/k4MbKgdlP6dbYY5ihw6yizXk10libjfcMQMK9zn1VUsm8ZO77690WmeHvti2+OU gvSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=vERzpTd8PFyshf2pm/39BUZZNvqkHOHkVNwWtxqM1k4=; b=l4XFYlEP4nIzwaE7K2EvtdG16QEb6PlIyFQqLG9PUdRFw/N+tl/fMFzra987KkKX9z +bF+I/1KoOr0XDsii/Wwu2k5pTCA3uUKspBOpXVmulR2ztmee7mkNQwOQn1ov5WGKRrU 3rXO+jU7YCEc03VlhIDPuFO2DSiVQazb+AvVa766fzNQdJoGuwJaCAUlQEI3w4BhuP5r dKXZ5cGD0JSG1C88gjG5hahGITi+AVgh2k/esChXEVTEWmIhcMZ5ZlqaamjPnlm1HBGu IyNjkuhgFU71MrLjqeh7act+ymT5Y5B/4Q+TKKvbwNZpPe9E+S8pCYG6kVdGnWnwEyEI /JrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b9p42Az8; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33-v6si22893275plh.50.2018.10.18.18.11.02; Thu, 18 Oct 2018 18:11:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b9p42Az8; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbeJSJOn (ORCPT + 10 others); Fri, 19 Oct 2018 05:14:43 -0400 Received: from mail-yw1-f68.google.com ([209.85.161.68]:41902 "EHLO mail-yw1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726245AbeJSJOn (ORCPT ); Fri, 19 Oct 2018 05:14:43 -0400 Received: by mail-yw1-f68.google.com with SMTP id 135-v6so12574902ywo.8 for ; Thu, 18 Oct 2018 18:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vERzpTd8PFyshf2pm/39BUZZNvqkHOHkVNwWtxqM1k4=; b=b9p42Az8SLZnMrei5M0Z/irgkHo4HigCpgizRZffM97//DBy0PmLb1b85anZfafMca ecxM74uheGMCpJkRHt7L8eK6m0XgogAVzABbRprH4LZgiyCstDQbsuwZ4MlD/yYsmToi Upbf4wXhqoYt5PxHoCQSDGQcIzwPsgvZL3g+w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vERzpTd8PFyshf2pm/39BUZZNvqkHOHkVNwWtxqM1k4=; b=Jl6TYF70OwSg5ATzwrTYuyOMq4IBiUoYnuLzxXes7QumcewYDiw+kSLEzrwbd6KHYR BtTzhP3I3NLv+rtadzbLfn+ulPaIpF4h1IF6nopcliNa1/ShxrmQxYdkdtjLAJwJF9F5 v6d0AqYHZoGiR9Zknoq9mP5KZWUG/M2GWlR0Mo9GG0r1g+dN9174+2zKZ8qlt0N1/wFC hat4HhssBTFoxood+AIoBCOtcfp1c+bgmVaQW3IerLhGSQufyeGDPs5kK84jkUmZRbtE DdLzXTr2K7BKIeXsQlXfWa38APIyXzNvo89pp2z9B4mt8k3I12aOPeAZzWlS6msbdFvI QsIw== X-Gm-Message-State: ABuFfoiRaoquI+3BVQBQZtITc11C3g81BSRIf6rXVcWh2OErn5GStOF5 jNXKZ/Irbpc2AWxS5Gw99FwM9JpomoE= X-Received: by 2002:a81:4a55:: with SMTP id x82-v6mr21252592ywa.3.1539911459131; Thu, 18 Oct 2018 18:10:59 -0700 (PDT) Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id n7-v6sm5481622ywb.8.2018.10.18.18.10.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 18:10:58 -0700 (PDT) From: masahisa.kojima@linaro.org To: netdev@vger.kernel.org Cc: ilias.apalodimas@linaro.org, jaswinder.singh@linaro.org, ard.biesheuvel@linaro.org, osaki.yoshitoyo@socionext.com, Masahisa Kojima Subject: [PATCH 2/3] net: socionext: Add dummy PHY register read in phy_write() Date: Fri, 19 Oct 2018 10:08:42 +0900 Message-Id: <20181019010843.3605-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20181019010843.3605-1-masahisa.kojima@linaro.org> References: <20181019010843.3605-1-masahisa.kojima@linaro.org> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Masahisa Kojima There is a compatibility issue between RTL8211E implemented in Developerbox and netsec network controller IP(F_GMAC4). RTL8211E expects MDC clock must be kept toggling for several clock cycle with MDIO high before entering the IDLE state. To meet this requirement, netsec driver needs to issue dummy read(e.g. read PHYID1(offset 0x2) register) right after write. Signed-off-by: Masahisa Kojima Signed-off-by: Yoshitoyo Osaki --- drivers/net/ethernet/socionext/netsec.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 2.14.2 diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index 273cc5fc07e0..e7faaf8be99e 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -431,9 +431,12 @@ static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) return 0; } +static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); + static int netsec_phy_write(struct mii_bus *bus, int phy_addr, int reg, u16 val) { + int status; struct netsec_priv *priv = bus->priv; if (netsec_mac_write(priv, GMAC_REG_GDR, val)) @@ -446,8 +449,19 @@ static int netsec_phy_write(struct mii_bus *bus, GMAC_REG_SHIFT_CR_GAR))) return -ETIMEDOUT; - return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, - NETSEC_GMAC_GAR_REG_GB); + status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, + NETSEC_GMAC_GAR_REG_GB); + + /* Developerbox implements RTL8211E PHY and there is + * a compatibility problem with F_GMAC4. + * RTL8211E expects MDC clock must be kept toggling for several + * clock cycle with MDIO high before entering the IDLE state. + * To meet this requirement, netsec driver needs to issue dummy + * read(e.g. read PHYID1(offset 0x2) register) right after write. + */ + netsec_phy_read(bus, phy_addr, 2); + + return status; } static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)