From patchwork Tue Oct 23 11:24:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 149439 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp568468ljp; Tue, 23 Oct 2018 04:26:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV62JQZHPFzbSvTIAHIArqnrH62AqktoWbWqs0AYXw2vM/SM5/r1GGrRHyiB5OWRH7IRpxkdb X-Received: by 2002:a17:902:5602:: with SMTP id h2-v6mr47612160pli.220.1540293994370; Tue, 23 Oct 2018 04:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540293994; cv=none; d=google.com; s=arc-20160816; b=vhwVVPc5QlinNMtiNFc+tIcQSS1qsvRm//6Q3hzacHhinR9fHEOUXHP3F1TyZq4s4/ hvMWVonUocUedR0gJV21D/KgRHKKmi6+t6TFjDPd6SLzKDAVElIoeBUYRds1v7TFa3nK ulJPELPgvdI6a7Pu/mrGnUnv9CK2Ft0ypbA4EOYVfeO5LWRXCNcIR2DVNwzyjafYq2Ux nas/6tHvts28IBLzh9s9Md76OcQDpV11sEg4IZVr7KSljEKpwTVMp4v4kpiQL9S1iVsh St8maYFv1hwYwq4cWLzOdKuARNBLd9JeQ8jR1RvBFxla16yvn7w+o0Fp+yurgQ5Jke1o JlsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=TUOW2QcqudOMU4++YbfL/YAuhSN/xUw3L01BavBZE5E=; b=Gg6lcrknChzHVnt6aHMDjMl7cOl/OK7dxjLSC9Ju5f1UZnWUxw5eyTPuu0LCDskXCj ezXSg99WSsCl5Zj8tjcaxF3VQf3PErQnu2o6u751jqt4ZBJEGDVod7rHv+mlcMJmUECq LibAHVL5gWBQJ4JPGAOr7CQZg3kdO2f3cuu+8RKWzzOa5f96bdre11y7346cPWlll5K6 /B2gYdTIfGlAahaOEhhf4pz8PDVA4r9ZScag17+2OW2HWqx7P5I25JLvrMt9I+nh6jbt 6KoNDii37JWaKDbPJ8L61KKppoU+Sf/JnRmhCfnH1J8Onq2kRfeFKzsmyMxpjUnhGe/U //tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FztF2Bti; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j20-v6si1056098pgl.279.2018.10.23.04.26.34; Tue, 23 Oct 2018 04:26:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FztF2Bti; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728186AbeJWTtf (ORCPT + 10 others); Tue, 23 Oct 2018 15:49:35 -0400 Received: from mail-yw1-f67.google.com ([209.85.161.67]:35499 "EHLO mail-yw1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727873AbeJWTtf (ORCPT ); Tue, 23 Oct 2018 15:49:35 -0400 Received: by mail-yw1-f67.google.com with SMTP id y76-v6so379551ywd.2 for ; Tue, 23 Oct 2018 04:26:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TUOW2QcqudOMU4++YbfL/YAuhSN/xUw3L01BavBZE5E=; b=FztF2BtiAnBbqmOffMBJShpr+rJb/PpbZiBMXN9NConSEeV1v+GnVj1fkPMdSgwOs5 2z1V99c2cGSTDpy5bR/rDw7pQTsbHjcWD8UpZLMrQrPCV1cv3e64xU4uVfpPbhImQzFm BH2hwbwdzLbqJttSazglUNSSOAvW/KWhkmt78= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TUOW2QcqudOMU4++YbfL/YAuhSN/xUw3L01BavBZE5E=; b=VFRI8zyhGcRyAaMylU0ZOtUgWajAmRmLc3Sbe4OCNQDeTyE2DDPU4aljoakS+RG9zO hgYFt4I7okfiBpw1I5Qo6IJvpbicyxe/Hap5S5R+u62Jrg6UGMKblC4kSqTvqwrrr1rz K2x8E0wXZL5Fddeo6Dw8HIL4ibsfZMtEr2qq5MfLCjpjTHtldBXp4lTXuHzPs5oM6eUH GJKmRCxT7S5LyVJmwKpZknUHdeRUWH3cact3CunqKVnOfSYa9BZnuYzUyaWebKPK1LHr JVUuupEWXDBSQCcb+pJQXFVMtO9W4ZlvojGOYhPE4F5e6XMVjeBD0YIV6qSfZwffNv9a 6JgQ== X-Gm-Message-State: ABuFfojqos9vTi4Xpb9K+/lYcmDnm2I/Z5ecc9VUtWwadPnPlotAVuvE dw6BwqmCHOcn9P+z5jpzli+v0fnzMN8= X-Received: by 2002:a81:3217:: with SMTP id y23-v6mr13898713ywy.509.1540293991750; Tue, 23 Oct 2018 04:26:31 -0700 (PDT) Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id e128-v6sm213262ywd.77.2018.10.23.04.26.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 04:26:31 -0700 (PDT) From: masahisa.kojima@linaro.org To: netdev@vger.kernel.org Cc: ilias.apalodimas@linaro.org, jaswinder.singh@linaro.org, ard.biesheuvel@linaro.org, osaki.yoshitoyo@socionext.com, Masahisa Kojima Subject: [PATCH net v2 2/3] net: socionext: Add dummy PHY register read in phy_write() Date: Tue, 23 Oct 2018 20:24:27 +0900 Message-Id: <20181023112428.6785-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20181023112428.6785-1-masahisa.kojima@linaro.org> References: <20181023112428.6785-1-masahisa.kojima@linaro.org> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Masahisa Kojima There is a compatibility issue between RTL8211E implemented in Developerbox and netsec ethernet controller IP. Our MDIO controller stops MDC clock right after the write access, but RTL8211E expects MDC clock must be kept toggling for several clock cycle with MDIO high before entering the IDLE state. Without keeping clock after write access, write access is not correctly handled and register is not updated. To meet this requirement, netsec driver needs to issue dummy read(e.g. read PHYID1(offset 0x2) register) right after write access, to keep MDC clock. We think this compatibility issue is a problem specific to our MDIO controller and RTL8211E. Fixes: 533dd11a12f6 ("net: socionext: Add Synquacer NetSec driver") Signed-off-by: Masahisa Kojima Signed-off-by: Yoshitoyo Osaki --- changes in v2: - use the MACROs defiend in include/uapi/linux/mii.h drivers/net/ethernet/socionext/netsec.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 2.14.2 diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index 829ed2718b22..5c295cc0b8f8 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -432,9 +432,12 @@ static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) return 0; } +static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr); + static int netsec_phy_write(struct mii_bus *bus, int phy_addr, int reg, u16 val) { + int status; struct netsec_priv *priv = bus->priv; if (netsec_mac_write(priv, GMAC_REG_GDR, val)) @@ -447,8 +450,19 @@ static int netsec_phy_write(struct mii_bus *bus, GMAC_REG_SHIFT_CR_GAR))) return -ETIMEDOUT; - return netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, - NETSEC_GMAC_GAR_REG_GB); + status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, + NETSEC_GMAC_GAR_REG_GB); + + /* Developerbox implements RTL8211E PHY and there is + * a compatibility problem with F_GMAC4. + * RTL8211E expects MDC clock must be kept toggling for several + * clock cycle with MDIO high before entering the IDLE state. + * To meet this requirement, netsec driver needs to issue dummy + * read(e.g. read PHYID1(offset 0x2) register) right after write. + */ + netsec_phy_read(bus, phy_addr, MII_PHYSID1); + + return status; } static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)