From patchwork Wed Oct 31 18:13:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149853 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7126734ljp; Wed, 31 Oct 2018 11:15:45 -0700 (PDT) X-Google-Smtp-Source: AJdET5c8CFlRQsSJ52aeds3/+PfX66Fb9EoMYollAhnUa9wQ5p8dq3K0yaWNMI4hJvDUUlQIt8z6 X-Received: by 2002:a0d:e28c:: with SMTP id l134-v6mr4184946ywe.242.1541009745146; Wed, 31 Oct 2018 11:15:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541009745; cv=none; d=google.com; s=arc-20160816; b=q9eKC/I+ChkWvj1/jhcv4kmYtOzeSLljEbt8i7WuJZ+L0PzSn4aUMDuyMegPOvfPyM npuKXSf2EAwSdtm2L6F3L/JB/K8yiXP4HXJtHv5DfQQWJy52CR9Juz2pi1GYmBhR1Ojx Y3qZxvz2L7Ta/V7CAEffxH8nzPMzzfrquwgz55o1btRxszShSb3GJGztlzOM0Sm6DEqi HS/Zgd3cG0bOSGemnFUPIySZmgtyC8LCHFvEqnGH0f7sCCk0R59DlKcBEGGInkq6supb BPhrOMsg3DlA4SgEXwlGjkl1MG1mwt8pbcOfwiZPdwiM90QWTZVoMkUMX72OylsRSAoD bkiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=WVw5ao68efZ7aBPOVI8VEsWvM58ND7SaCN5GChDsKko=; b=vXSeJA4qd05GwQkTCuDCtCjQbtSgH3DSLly/aEfvNEOF93X2M7ve9mXt3WM/iNZRYh rGcpCM4g4ng31hPjDmH9nECJaaybD6FaUfK/vCgTyM+hfsPkL+uAAq3sjj3QxxfHn9qZ 34xygkymwEF3GHH5rzhHK52cAbYEqTfSkppvRhC/UdpzG9Y6PX9T082hi03GgIVoFS2f zZNlErFseLwSIhNU2ZvLpkEK1fOTDb+cFSpdJDv6oH9+gaO4bSRfbqngkzJEDXPPV8SV 37Vyd9eYUWAGMkcaaGXvyjEvx5pW47ik45wUeBG+J1cn36+LlY8FLvILtP/6m5gQV6Lq cXpw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id j188-v6si5305785ybc.485.2018.10.31.11.15.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Oct 2018 11:15:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gHuzm-0004R7-Fx; Wed, 31 Oct 2018 18:13:34 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gHuzl-0004Py-3i for xen-devel@lists.xen.org; Wed, 31 Oct 2018 18:13:33 +0000 X-Inumbo-ID: acb946f3-dd38-11e8-87d6-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id acb946f3-dd38-11e8-87d6-bc764e045a96; Wed, 31 Oct 2018 18:13:32 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC7C51596; Wed, 31 Oct 2018 11:13:31 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0CD673F6A8; Wed, 31 Oct 2018 11:13:30 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 31 Oct 2018 18:13:02 +0000 Message-Id: <20181031181313.8028-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181031181313.8028-1-julien.grall@arm.com> References: <20181031181313.8028-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 10/21] xen/arm: Move SYSREG accessors in sysregs.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andrii_anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" System registers accessors are self-contained and should not be included everywhere in Xen. Move the accessors in sysregs.h and include the file when necessary. With that change, it is not necessary to include processor.h in time.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/arm32/entry.S | 1 + xen/arch/arm/arm32/proc-v7.S | 1 + xen/arch/arm/gic-v3-lpi.c | 1 + xen/arch/arm/gic-v3.c | 1 + xen/include/asm-arm/arm32/processor.h | 62 ----------------------------- xen/include/asm-arm/arm32/sysregs.h | 74 +++++++++++++++++++++++++++++++++++ xen/include/asm-arm/arm64/processor.h | 25 ------------ xen/include/asm-arm/arm64/sysregs.h | 23 +++++++++++ xen/include/asm-arm/page.h | 1 + xen/include/asm-arm/percpu.h | 8 +--- xen/include/asm-arm/sysregs.h | 22 +++++++++++ xen/include/asm-arm/time.h | 2 +- 12 files changed, 126 insertions(+), 95 deletions(-) create mode 100644 xen/include/asm-arm/arm32/sysregs.h create mode 100644 xen/include/asm-arm/sysregs.h diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index f6908e3f16..0b4cd19abd 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -1,4 +1,5 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S index 2f3ff1e6c9..80a250d8e8 100644 --- a/xen/arch/arm/arm32/proc-v7.S +++ b/xen/arch/arm/arm32/proc-v7.S @@ -19,6 +19,7 @@ #include #include +#include ca15mp_init: ca7mp_init: diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index efd5cd62fb..e8c6e159ca 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -30,6 +30,7 @@ #include #include #include +#include /* * There could be a lot of LPIs on the host side, and they always go to diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a7ce94789c..264a981bab 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -42,6 +42,7 @@ #include #include #include +#include /* Global state */ static struct { diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index fb330812af..4e679f3273 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H -#include - #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ @@ -60,66 +58,6 @@ struct cpu_user_regs #endif -/* Layout as used in assembly, with src/dest registers mixed in */ -#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 -#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm -#define CP32(r, name...) __CP32(r, name) -#define CP64(r, name...) __CP64(r, name) - -/* Stringified for inline assembly */ -#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" -#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" -#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" -#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" - -/* Issue a CP operation which takes no argument, - * uses r0 as a placeholder register. */ -#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" - -#ifndef __ASSEMBLY__ - -/* C wrappers */ -#define READ_CP32(name...) ({ \ - register uint32_t _r; \ - asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP32(v, name...) do { \ - register uint32_t _r = (v); \ - asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ -} while (0) - -#define READ_CP64(name...) ({ \ - register uint64_t _r; \ - asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP64(v, name...) do { \ - register uint64_t _r = (v); \ - asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ -} while (0) - -/* - * C wrappers for accessing system registers. - * - * Registers come in 3 types: - * - those which are always 32-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG32). - * - those which are always 64-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG64). - * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). - */ -#define READ_SYSREG32(R...) READ_CP32(R) -#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) - -#define READ_SYSREG64(R...) READ_CP64(R) -#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) - -#define READ_SYSREG(R...) READ_SYSREG32(R) -#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) - -#endif /* __ASSEMBLY__ */ - #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ /* * Local variables: diff --git a/xen/include/asm-arm/arm32/sysregs.h b/xen/include/asm-arm/arm32/sysregs.h new file mode 100644 index 0000000000..b25b59a557 --- /dev/null +++ b/xen/include/asm-arm/arm32/sysregs.h @@ -0,0 +1,74 @@ +#ifndef __ASM_ARM_ARM32_SYSREGS_H +#define __ASM_ARM_ARM32_SYSREGS_H + +#include + +/* Layout as used in assembly, with src/dest registers mixed in */ +#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 +#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm +#define CP32(r, name...) __CP32(r, name) +#define CP64(r, name...) __CP64(r, name) + +/* Stringified for inline assembly */ +#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" +#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" +#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" +#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" + +/* Issue a CP operation which takes no argument, + * uses r0 as a placeholder register. */ +#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" + +#ifndef __ASSEMBLY__ + +/* C wrappers */ +#define READ_CP32(name...) ({ \ + register uint32_t _r; \ + asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP32(v, name...) do { \ + register uint32_t _r = (v); \ + asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ +} while (0) + +#define READ_CP64(name...) ({ \ + register uint64_t _r; \ + asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP64(v, name...) do { \ + register uint64_t _r = (v); \ + asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ +} while (0) + +/* + * C wrappers for accessing system registers. + * + * Registers come in 3 types: + * - those which are always 32-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG32). + * - those which are always 64-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG64). + * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). + */ +#define READ_SYSREG32(R...) READ_CP32(R) +#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) + +#define READ_SYSREG64(R...) READ_CP64(R) +#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) + +#define READ_SYSREG(R...) READ_SYSREG32(R) +#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARM_ARM32_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index c18ab7203d..765de1b74b 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,8 +3,6 @@ #include -#include - #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ @@ -89,29 +87,6 @@ struct cpu_user_regs #undef __DECL_REG -/* Access to system registers */ - -#define READ_SYSREG32(name) ({ \ - uint32_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) -#define WRITE_SYSREG32(v, name) do { \ - uint32_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) - -#define WRITE_SYSREG64(v, name) do { \ - uint64_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) -#define READ_SYSREG64(name) ({ \ - uint64_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) - -#define READ_SYSREG(name) READ_SYSREG64(name) -#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index f510925a2a..08585a969e 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,29 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +/* Access to system registers */ + +#define READ_SYSREG32(name) ({ \ + uint32_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) +#define WRITE_SYSREG32(v, name) do { \ + uint32_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) + +#define WRITE_SYSREG64(v, name) do { \ + uint64_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) +#define READ_SYSREG64(name) ({ \ + uint64_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) + +#define READ_SYSREG(name) READ_SYSREG64(name) +#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index bcdea970ca..1a1713ce02 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -4,6 +4,7 @@ #include #include #include +#include #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index cdf64e0f77..6263e77251 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,13 +4,7 @@ #ifndef __ASSEMBLY__ #include -#if defined(CONFIG_ARM_32) -# include -#elif defined(CONFIG_ARM_64) -# include -#else -# error "unknown ARM variant" -#endif +#include extern char __per_cpu_start[], __per_cpu_data_end[]; extern unsigned long __per_cpu_offset[NR_CPUS]; diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h new file mode 100644 index 0000000000..5c5c51bbcd --- /dev/null +++ b/xen/include/asm-arm/sysregs.h @@ -0,0 +1,22 @@ +#ifndef __ASM_ARM_SYSREGS_H +#define __ASM_ARM_SYSREGS_H + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ASM_ARM_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + + diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index ea88e76304..9a7071a546 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -1,7 +1,7 @@ #ifndef __ARM_TIME_H__ #define __ARM_TIME_H__ -#include +#include #define DT_MATCH_TIMER \ DT_MATCH_COMPATIBLE("arm,armv7-timer"), \