From patchwork Wed Nov 7 16:43:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 150427 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp5387362ljp; Wed, 7 Nov 2018 08:44:20 -0800 (PST) X-Received: by 2002:aed:2603:: with SMTP id z3mr960671qtc.120.1541609059945; Wed, 07 Nov 2018 08:44:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541609059; cv=none; d=google.com; s=arc-20160816; b=ANYDbbLPiiUeZRWxZpmxoQEIwoZjEiV6E8QHO7x0dyTVjJd3mngPb5i6qgmshlZDbv q1dIP4VP9k0g3dEm4wbfrLfqn4J8Ib8lcDH37J8/dFipYdUrFVyIJ+gE7/Zk7DunI4CP Vll27kh9DXVZf842KHPgzwXtCOw8xV3967sVqfHCHG7dtLi4AYdISMmruPdzr8LC8Osp FFrB5WLtvb39VbBNCuohQtgPcNTZQqb1KxrSfgQ8uRyNfhkKwuT3FU1olGQ/mwDitGIN 3P0T7ETeHo/iatO+mY2U7ydEUCxbR392XPOWlADmV9ztgE67oOzeovuakjPbFv2LPF6O dEIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mD0BlP8oF5vxWXlv0istyEBrd98DbpzGJVe7ViiydmE=; b=b8O11yssG9ZFUDy14MJdBMtnr8NNcw6HCcvnTzdwGbdYyb8qbcK3qb5mJolsShjixo appAA2nLMKzgYx90sicz4bcs8WsVkeyJWqoOmf0XINovdT1ONGbqNqxuBx26mwYXqt+J nWO8QDEpWl2mV2P7j5xmF2eDOTfS0VLYl99UrvXFeD+W3xgAthFVjePdd7h8nnSDGIE6 891OsKB3CogAWUaH1Zn7BsHMmxNRiDD+Cx5IhjlaqRpQ2lV6RNk3dffB4x3HjZyWGbya fNXW1Tu6ZnAbysw0Qwwite+OJ/rR1lxYSTn9bBh4yuWpnSKw/M2jYb9BsSc43EW2OrN3 s69Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O/UWwInS"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id g136sor583945qka.19.2018.11.07.08.44.19 for (Google Transport Security); Wed, 07 Nov 2018 08:44:19 -0800 (PST) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O/UWwInS"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mD0BlP8oF5vxWXlv0istyEBrd98DbpzGJVe7ViiydmE=; b=O/UWwInSH2bipm9tjByUuJu8zaV7crR/uMhrEnjTXYCrhLWIyhFs3lfL8/186rEGgs AUKBLQl1Bc6sMJylJwyOtWFiNugmNHDZKvD+oOSk3RCrGTlzS6dtigI5leqSF7LToU7j NW8xqYMH7ghdmSeBAJh9z0VWBLTCpsDeNL6wc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mD0BlP8oF5vxWXlv0istyEBrd98DbpzGJVe7ViiydmE=; b=T45J1XfbL83oiNRAmtC1/g/YGnhLSNh4ewiQFQOAgSyBF56Y52mhUjomw4zjGWk1e0 dn8ZIrMpzVOVxXub2kPFaZGyYX/JOKpVhQkz/th3PsRqrAY55c/dp2L8MgdC6dPt6wz2 Hf8Fseq2B4I2PskGyklq81+rgD4iM0chFFlpPD8ucndYoQhOFWKjTj9Z2xAtAJ50KrsL 518PX0+s+0m2hUd6d1PXSoWD1otmTsrKKFtkchy/EoLyHji12FuVBYli09gufuB79HUH Mw7NFccCVF46Q/jeO+kc6y0oCPxnjJIxILccRlqMFKlDqC/JkhmVHr7Z70uM2PsXu4Ok 4MBA== X-Gm-Message-State: AGRZ1gI0Rah/XEdBxmEndVQuPo7euSeVRaee/CFHxv9DVf7AFHJZsYU7 W13PUV/qUSVNZWtjjOXHMkYQw1gi X-Google-Smtp-Source: AJdET5enTvj7T05sN7bAvu1IvIt24N4m36GdZaPZeDEnpO0fD1mT+hHqZugodUqyl2U5DT6ggFDvrQ== X-Received: by 2002:a37:a1c1:: with SMTP id k184mr888076qke.166.1541609059410; Wed, 07 Nov 2018 08:44:19 -0800 (PST) Return-Path: Received: from localhost.localdomain (pool-72-71-243-63.cncdnh.fast00.myfairpoint.net. [72.71.243.63]) by smtp.googlemail.com with ESMTPSA id 96-v6sm681817qtc.56.2018.11.07.08.44.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Nov 2018 08:44:18 -0800 (PST) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.9 V2 12/24] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Date: Wed, 7 Nov 2018 11:43:50 -0500 Message-Id: <20181107164402.9380-13-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181107164402.9380-1-dave.long@linaro.org> References: <20181107164402.9380-1-dave.long@linaro.org> From: Marc Zyngier Commit 0c47ac8cd157727e7a532d665d6fb1b5fd333977 upstream. In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm/kvm/hyp/hyp-entry.S | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 625edef2a54f..3ad2c44f4137 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -257,6 +257,11 @@ static inline void *kvm_get_hyp_vector(void) return kvm_ksym_ref(__kvm_hyp_vector_bp_inv); } + case ARM_CPU_PART_CORTEX_A15: + { + extern char __kvm_hyp_vector_ic_inv[]; + return kvm_ksym_ref(__kvm_hyp_vector_ic_inv); + } #endif default: { diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S index 58ec002721a1..1bdd03014138 100644 --- a/arch/arm/kvm/hyp/hyp-entry.S +++ b/arch/arm/kvm/hyp/hyp-entry.S @@ -72,6 +72,28 @@ __kvm_hyp_vector: W(b) hyp_fiq #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + .align 5 +__kvm_hyp_vector_ic_inv: + .global __kvm_hyp_vector_ic_inv + + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + W(add) sp, sp, #1 /* Reset 7 */ + W(add) sp, sp, #1 /* Undef 6 */ + W(add) sp, sp, #1 /* Syscall 5 */ + W(add) sp, sp, #1 /* Prefetch abort 4 */ + W(add) sp, sp, #1 /* Data abort 3 */ + W(add) sp, sp, #1 /* HVC 2 */ + W(add) sp, sp, #1 /* IRQ 1 */ + W(nop) /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + .align 5 __kvm_hyp_vector_bp_inv: .global __kvm_hyp_vector_bp_inv @@ -92,6 +114,8 @@ __kvm_hyp_vector_bp_inv: mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: + #ifdef CONFIG_THUMB2_KERNEL /* * Yet another silly hack: Use VPIDR as a temp register.