[1/3] dt-bindings: soc: qcom: Add AOSS QMP binding

Message ID 20181112080557.22698-2-bjorn.andersson@linaro.org
State New
Headers show
Series
  • Qualcomm AOSS QMP side channel binding and driver
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Commit Message

Bjorn Andersson Nov. 12, 2018, 8:05 a.m.
Add binding for the QMP based side-channel communication mechanism to
the AOSS, which is used to control resources not exposed through the
RPMh interface.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

---
 .../bindings/soc/qcom/qcom,aoss-qmp.txt       | 63 +++++++++++++++++++
 include/dt-bindings/power/qcom-aoss-qmp.h     | 15 +++++
 2 files changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
 create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h

-- 
2.18.0

Comments

Rob Herring Dec. 3, 2018, 11:51 p.m. | #1
On Mon, Nov 12, 2018 at 12:05:55AM -0800, Bjorn Andersson wrote:
> Add binding for the QMP based side-channel communication mechanism to

> the AOSS, which is used to control resources not exposed through the

> RPMh interface.

> 

> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---

>  .../bindings/soc/qcom/qcom,aoss-qmp.txt       | 63 +++++++++++++++++++

>  include/dt-bindings/power/qcom-aoss-qmp.h     | 15 +++++

>  2 files changed, 78 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt

>  create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h

> 

> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt

> new file mode 100644

> index 000000000000..e3c8cb4372f2

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt

> @@ -0,0 +1,63 @@

> +Qualcomm Always-On Subsystem side channel binding

> +

> +This binding describes the hardware component responsible for side channel

> +requests to the always-on subsystem (AOSS), used for certain power management

> +requests that is not handled by the standard RPMh interface. Each client in the

> +SoC has it's own block of message RAM and IRQ for communication with the AOSS.

> +The protocol used to communicate in the message RAM is known as QMP.

> +

> +- compatible:

> +	Usage: required

> +	Value type: <string>

> +	Definition: must be "qcom,sdm845-aoss-qmp"

> +

> +- reg:

> +	Usage: required

> +	Value type: <prop-encoded-array>

> +	Definition: the base address and size of the message RAM for this

> +		    client's communication with the AOSS

> +

> +- interrupts:

> +	Usage: required

> +	Value type: <prop-encoded-array>

> +	Definition: should specify the AOSS message IRQ for this client

> +

> +- mboxes:

> +	Usage: required

> +	Value type: <prop-encoded-array>

> +	Definition: reference to the mailbox representing the outgoing doorbell

> +		    in APCS for this client, as described in mailbox/mailbox.txt

> +

> += AOSS Power-domains

> +The AOSS side channel exposes control over a set of resources, used to control

> +a set of debug related clocks and to affect the low power state of resources

> +related to the secondary subsystems. These resources are described as a set of

> +power-domains in a subnode of hte AOSS side channel node.


Why does this need to be a sub-node? Are there other sub-nodes needed?

> +

> +- compatible:

> +	Usage: required

> +	Value type: <string>

> +	Definition: must be "qcom,sdm845-aoss-qmp-pd"

> +

> +- #power-domain-cells:

> +	Usage: required

> +	Value type: <u32>

> +	Definition: must be 1
Doug Anderson Dec. 10, 2018, 11:56 p.m. | #2
Hi,

On Mon, Nov 12, 2018 at 12:02 AM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> +  aoss_qmp: qmp@c300000 {

> +          compatible = "qcom,sdm845-aoss-qmp";

> +          reg = <0x0c300000 0x100000>;


drive-by nit: s/0x0c300000/0xc300000

...another random suggestion is that I think Rob H. has been
requesting that examples have the #include in them...

-Doug

Patch

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
new file mode 100644
index 000000000000..e3c8cb4372f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
@@ -0,0 +1,63 @@ 
+Qualcomm Always-On Subsystem side channel binding
+
+This binding describes the hardware component responsible for side channel
+requests to the always-on subsystem (AOSS), used for certain power management
+requests that is not handled by the standard RPMh interface. Each client in the
+SoC has it's own block of message RAM and IRQ for communication with the AOSS.
+The protocol used to communicate in the message RAM is known as QMP.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,sdm845-aoss-qmp"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: the base address and size of the message RAM for this
+		    client's communication with the AOSS
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the AOSS message IRQ for this client
+
+- mboxes:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: reference to the mailbox representing the outgoing doorbell
+		    in APCS for this client, as described in mailbox/mailbox.txt
+
+= AOSS Power-domains
+The AOSS side channel exposes control over a set of resources, used to control
+a set of debug related clocks and to affect the low power state of resources
+related to the secondary subsystems. These resources are described as a set of
+power-domains in a subnode of hte AOSS side channel node.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,sdm845-aoss-qmp-pd"
+
+- #power-domain-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 1
+
+= EXAMPLE
+
+The following example represents the AOSS side-channel message RAM and the
+mechanism exposing the power-domains, as found in SDM845.
+
+  aoss_qmp: qmp@c300000 {
+          compatible = "qcom,sdm845-aoss-qmp";
+          reg = <0x0c300000 0x100000>;
+          interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+
+          mboxes = <&apss_shared 0>;
+
+          aoss_qmp_pd: power-controller {
+                  compatible = "qcom,sdm845-aoss-qmp-pd";
+                  #power-domain-cells = <1>;
+          };
+  };
diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h
new file mode 100644
index 000000000000..7d8ac1a4f90c
--- /dev/null
+++ b/include/dt-bindings/power/qcom-aoss-qmp.h
@@ -0,0 +1,15 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, Linaro Ltd. */
+
+#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
+#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H
+
+#define AOSS_QMP_QDSS_CLK	0
+#define AOSS_QMP_LS_CDSP		1
+#define AOSS_QMP_LS_LPASS	2
+#define AOSS_QMP_LS_MODEM	3
+#define AOSS_QMP_LS_SLPI		4
+#define AOSS_QMP_LS_SPSS		5
+#define AOSS_QMP_LS_VENUS	6
+
+#endif