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[209.132.180.67]) by mx.google.com with ESMTP id h68-v6si19277640pfb.142.2018.11.12.06.12.56; Mon, 12 Nov 2018 06:12:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="c9l3U/2d"; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729426AbeKMAGW (ORCPT + 5 others); Mon, 12 Nov 2018 19:06:22 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:39205 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727103AbeKMAGW (ORCPT ); Mon, 12 Nov 2018 19:06:22 -0500 Received: by mail-lf1-f65.google.com with SMTP id n18so6274095lfh.6 for ; Mon, 12 Nov 2018 06:12:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xfe46Bmt0854EQhFRugeAp0o8UPMhV6L1Gu8vX/QvIg=; b=c9l3U/2dQOsUCgj8BbxfoO1yESceLkvc6v7qoWiFGZKRwjtsgfnrmk6jvclVFFuZSr Swr0+CzCXCHP2a1JnHgjuJuXS6MRUg2LTt1uE1Nwkgw1vNYkvby/x02nJx0Sbij/snjj 0Ry+ITxsc7Uu12MB6uLPLpkGImMr0wvLzde1s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xfe46Bmt0854EQhFRugeAp0o8UPMhV6L1Gu8vX/QvIg=; b=dpDlF8MYnZbN4dZH0CEUj/hmPBOjViC+SFIAu5nnenFz5dwoblADnYRSFBX0NM1vzs reEBJjGNYSVG2keDy71s8RhW90ZEL0i91kt79h8EuWI+K6wkRfH2JzPwkbk3sHgngKda fKnjOcE9IiQB7e9XdC0JMLedyYWg+CLymHpj7mHB1wJwFLdhjoeaBOaOH9q/Ptqe8RvA 287s6EDjb9JGDx5aSywZJDaGYmEATzTshuYI+cH5Z6kNmPejeYAIcuTfXNaQfu+G5qU0 rOF48DPEkw5oeiIERgfc+wjnOdTtgu8gagKEbrEoTF7EBdUMkqYuKjLee2kuqdoOiLcq aiTg== X-Gm-Message-State: AGRZ1gI+3YX2k4A6K1kzVdemtsm+Ks5VEFKprgUTHaMPJvPJc22qeWvq BMqBcTsMmbSvhPJWyfzI9BCylo4euwCsIQ== X-Received: by 2002:a19:d9d6:: with SMTP id s83mr741245lfi.57.1542031973074; Mon, 12 Nov 2018 06:12:53 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id m14-v6sm3056889lji.29.2018.11.12.06.12.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Nov 2018 06:12:52 -0800 (PST) From: Linus Walleij To: linux-mmc@vger.kernel.org, Ulf Hansson Cc: Linus Walleij , Paul Cercueil , linux-mips@linux-mips.org Subject: [PATCH 02/10] mmc: jz4740: Get CD/WP GPIOs from descriptors Date: Mon, 12 Nov 2018 15:12:31 +0100 Message-Id: <20181112141239.19646-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181112141239.19646-1-linus.walleij@linaro.org> References: <20181112141239.19646-1-linus.walleij@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Modifty the JZ4740 driver to retrieve card detect and write protect GPIO pins from GPIO descriptors instead of hard-coded global numbers. Augment the only board file using this in the process and cut down on passed in platform data. Preserve the code setting the caps2 flags for CD and WP as active low or high since the slot GPIO code currently ignores the gpiolib polarity inversion semantice and uses the raw accessors to read the GPIO lines, but set the right polarity flags in the descriptor table for jz4740. Cc: Paul Cercueil Cc: linux-mips@linux-mips.org Signed-off-by: Linus Walleij --- .../mips/include/asm/mach-jz4740/jz4740_mmc.h | 2 -- arch/mips/jz4740/board-qi_lb60.c | 12 ++++++++--- drivers/mmc/host/jz4740_mmc.c | 20 +++++++++---------- 3 files changed, 19 insertions(+), 15 deletions(-) -- 2.17.2 Acked-by: Paul Burton diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h index e9cc62cfac99..ff50aeb1a933 100644 --- a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h @@ -4,8 +4,6 @@ struct jz4740_mmc_platform_data { int gpio_power; - int gpio_card_detect; - int gpio_read_only; unsigned card_detect_active_low:1; unsigned read_only_active_low:1; unsigned power_active_low:1; diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index af0c8ace0141..705593d40d12 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -43,7 +43,6 @@ #include "clock.h" /* GPIOs */ -#define QI_LB60_GPIO_SD_CD JZ_GPIO_PORTD(0) #define QI_LB60_GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2) #define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x)) @@ -386,12 +385,18 @@ static struct platform_device qi_lb60_gpio_keys = { }; static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = { - .gpio_card_detect = QI_LB60_GPIO_SD_CD, - .gpio_read_only = -1, .gpio_power = QI_LB60_GPIO_SD_VCC_EN_N, .power_active_low = 1, }; +static struct gpiod_lookup_table qi_lb60_mmc_gpio_table = { + .dev_id = "jz4740-mmc.0", + .table = { + GPIO_LOOKUP("GPIOD", 0, "cd", GPIO_ACTIVE_HIGH), + { }, + }, +}; + /* beeper */ static struct pwm_lookup qi_lb60_pwm_lookup[] = { PWM_LOOKUP("jz4740-pwm", 4, "pwm-beeper", NULL, 0, @@ -500,6 +505,7 @@ static int __init qi_lb60_init_platform_devices(void) gpiod_add_lookup_table(&qi_lb60_audio_gpio_table); gpiod_add_lookup_table(&qi_lb60_nand_gpio_table); gpiod_add_lookup_table(&qi_lb60_spigpio_gpio_table); + gpiod_add_lookup_table(&qi_lb60_mmc_gpio_table); spi_register_board_info(qi_lb60_spi_board_info, ARRAY_SIZE(qi_lb60_spi_board_info)); diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index 0c1efd5100b7..44ea452add8e 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -983,17 +983,17 @@ static int jz4740_mmc_request_gpios(struct mmc_host *mmc, if (!pdata->read_only_active_low) mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; - if (gpio_is_valid(pdata->gpio_card_detect)) { - ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0); - if (ret) - return ret; - } + /* + * Get optional card detect and write protect GPIOs, + * only back out on probe deferral. + */ + ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); + if (ret == -EPROBE_DEFER) + return ret; - if (gpio_is_valid(pdata->gpio_read_only)) { - ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only); - if (ret) - return ret; - } + ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); + if (ret == -EPROBE_DEFER) + return ret; return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, "MMC read only", true, pdata->power_active_low);