From patchwork Fri Nov 16 06:56:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 151287 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp69248ljp; Thu, 15 Nov 2018 22:57:26 -0800 (PST) X-Google-Smtp-Source: AJdET5f3TuUZV1PWTxPraxsh8KbxEfkdMRsbvAoKula4w7uG08egU+FDONbWl9OaDTvfoeztGZ+7 X-Received: by 2002:a63:d547:: with SMTP id v7mr8675478pgi.339.1542351446200; Thu, 15 Nov 2018 22:57:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542351446; cv=none; d=google.com; s=arc-20160816; b=d8QXxQ+Zm4R4jUdUuFNUiqmXWj9nIsy/MiZJBgXP2RvcQBE2Jb4reRP7raVaJd4DCh 7y0PkdRDGUsXEoRnW0YF0s1FcfjPs1DTEQFAu0Aqe5hEDTKiLOADfA7kp1+woitfuyt8 cAR7IxzaEXPZCxU0xm8JjjR+ayjRRw8RpW00UqwJMZe3hAVbPkf4gJft/VfGTlRdL29r Q3ewemHgegbz3ItAG7WXE1tFQlq/Lv1SFqGlrqZhoePuuDccY8+YqI+tDKud1MN13xEH RSIuMrPNFvq6TfLAmFnf0/+l+ETpicPHVRZU5Bg+kya2+bOJ51K3PNBtzeClpjfTuyu/ gJLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=zYqensygLCGtbaMW1F7DQSvrp1D7xKpYSGDtQhc45Dc=; b=CddX0A5gK9HAneQ49AJbmMA2XwA4F8yTl3vwh/6ha3dFFmgi/UbubLgjducWB1abKy ZxduiIYXlgs1Ekfsd+gS/Izv63Cfz4k9vuzXKVJ34eP3WIFKhJQ9HWiqZ1JM1Q5c9kmM etlbykMuqKDiQ4+ODQux3ifZpzvthCpDZhsBahoW/MOhzkgq4AKmIgUCqiB+afQQZy2L mJ5e0GYZvITXba0ufKee3y5Aze+Gxj85y/gU0H9s/3zosQD82j59exwmVp+um8npMGQq Bh1br7v1cpR3cPxJ62MzzxalqB49SPKIh+oE6HdCbgtxN81S8k/XiDY0T6NOiS+mefOR NoZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dqKxCL5s; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id x1si8485438pfn.111.2018.11.15.22.57.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Nov 2018 22:57:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dqKxCL5s; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CCAF321191754; Thu, 15 Nov 2018 22:57:25 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 61B5D21191747 for ; Thu, 15 Nov 2018 22:57:24 -0800 (PST) Received: by mail-pf1-x441.google.com with SMTP id b85so4119108pfc.3 for ; Thu, 15 Nov 2018 22:57:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k1Sdk/UGeCNezio+VV+FBazIhS99Vhd9XOz8GyP8MlA=; b=dqKxCL5sf0Z0xxp/pV1tYkZHH8wZMV/oEoVJsO2GD6IC7PIwcO3J1+YFq3OKhLENql qOPsfAXugvFaMQvT1yLFZSbEnLjUyImlVm+u2evomY+Ep1J/xmN6mjXb+i9qOHCQE7jW R8G3ZaVC64LiEGAFp7Ay9T1oYMRtr/39KSvzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k1Sdk/UGeCNezio+VV+FBazIhS99Vhd9XOz8GyP8MlA=; b=NP7aFTx2kmym9LyiuRDxS59o9UV8i/mFQYy6NlMAylYpOPFdlalme1nBqEiXKz8ZYr jMYgLQk9Bj8AVhDwg6Mce8NOH6W4bNHMxYMKe1VXAtOZqZ2E+2oHFh6z1LX7dOHgVg5e IzLhKoitTcgxgD0N6VkYBlwAbQd9GSJtZdVOu5jTZnAhXrTJyivukNZ/ALjx1+MXAn1t wPHJS0X5pcz/UUXfSXYEVQBdod+5nsyhfKn1d18eKJtTFStyryZT+M3M/6atnK8yfJlO xtCujdFrTB5hCJ4EwQWOQd8m4MzIbaPRguWKS1sO0jaG0AZTkya7F4r9dvdxUVWI0WDr hoxA== X-Gm-Message-State: AGRZ1gI9zzQqSacXTe93JYOj5GsvuK+YGE1AqenCUybwCYfjzL9SbJxp iXzAyR6Lb7fLcDjMqlM/1uXMSbs+dmrVP4rP X-Received: by 2002:a63:9e58:: with SMTP id r24mr9059456pgo.264.1542351443731; Thu, 15 Nov 2018 22:57:23 -0800 (PST) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id h134sm2835905pfe.27.2018.11.15.22.57.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Nov 2018 22:57:23 -0800 (PST) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 16 Nov 2018 14:56:48 +0800 Message-Id: <20181116065702.30559-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20181116065702.30559-1-ming.huang@linaro.org> References: <20181116065702.30559-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 01/15] Hisilicon/D0x: Modify IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Main gist is reformatting some of the IORT into a form the current acpica-tools can handle, and also fix some bugfixes and closing of comment blocks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reported-by: Al Stone --- Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 24 +++++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 64 ++++++++++++-------- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 34 ++++------- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 6 +- 4 files changed, 71 insertions(+), 57 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index 929548514934..bb70dcd0c443 100644 --- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -282,11 +282,11 @@ /* RC 0 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -301,6 +301,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000000 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00000000 [0004] ID Count : 00002000 @@ -311,11 +313,11 @@ /* RC 1 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -330,6 +332,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 0000e000 [0004] ID Count : 00002000 @@ -340,11 +344,11 @@ /* RC 2 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -359,6 +363,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00008000 [0004] ID Count : 00002000 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 9955f6dbeb78..b64fcb4c7891 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -392,11 +392,11 @@ /*1P NA PCIe2 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -411,6 +411,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 0000f800 [0004] ID Count : 00000800 @@ -420,11 +422,11 @@ Single Mapping : 0 /* 1P NB PCIe0 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -439,6 +441,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000004 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00008800 [0004] ID Count : 00000800 @@ -449,11 +453,11 @@ /* 1P NB PCIe1 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -468,6 +472,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00007800 [0004] ID Count : 00000800 @@ -478,11 +484,11 @@ /* 1P NB PCIe2 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -497,6 +503,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000006 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 0000c000 [0004] ID Count : 00000800 @@ -506,11 +514,11 @@ Single Mapping : 0 /* 1P NB PCIe3 */ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -525,6 +533,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000007 + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00009000 [0004] ID Count : 00000800 @@ -534,11 +544,11 @@ Single Mapping : 0 /* 2P NA PCIe2*/ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -553,6 +563,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000a + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00001000 [0004] ID Count : 00001000 @@ -563,11 +575,11 @@ /* 2P NB PCIe0*/ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -582,6 +594,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000c + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00002000 [0004] ID Count : 00001000 @@ -592,11 +606,11 @@ /* 2P NB PCIe1*/ [0001] Type : 02 -[0002] Length : 0034 -[0001] Revision : 00 +[0002] Length : 0038 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000020 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -611,6 +625,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000d + Memory Size Limit : 00 + Reserved : 00000000 [0004] Input base : 00003000 [0004] ID Count : 00001000 diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl index 33b5d5250bd4..08e15c17bf40 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl @@ -53,9 +53,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 01 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000001 [0004] DeviceID mapping index : 00000002 [0004] Input base : 00000000 @@ -99,9 +97,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 01 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000001 [0004] DeviceID mapping index : 0001 [0004] Input base : 00007c00 @@ -139,9 +135,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 01 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000001 [0004] DeviceID mapping index : 00000001 [0004] Input base : 00007400 @@ -179,9 +173,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 03 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000003 [0004] DeviceID mapping index : 00000002 [0004] Input base : 00008000 @@ -225,9 +217,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 03 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000003 [0004] DeviceID mapping index : 0001 [0004] Input base : 0000BC00 @@ -265,9 +255,7 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -[0001] Proximity Domain : 03 -[0001] Reserved : 00 -[0002] Reserved : 0000 +[0004] Proximity Domain : 00000003 [0004] DeviceID mapping index : 00000001 [0004] Input base : 0000B400 @@ -287,10 +275,10 @@ /*0x2FC RC 0 */ [0001] Type : 02 [0002] Length : 00A0 -[0001] Revision : 00 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 0000000C -[0004] Mapping Offset : 00000028 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -305,6 +293,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000000 // should match with above MCFG + Memory Size Limit : 00 + Reserved : 00000000 /* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */ [0004] Input base : 00000000 @@ -322,7 +312,7 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1 -/* host2 and host3 should no open smmu for chips smmu bug * +/* host2 and host3 should no open smmu for chips smmu bug */ /* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */ [0004] Input base : 00007a00 [0004] ID Count : 00000100 // the number of IDs in range @@ -371,7 +361,7 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1 -/* host8 and host9 should no open smmu for chips smmu bug * +/* host8 and host9 should no open smmu for chips smmu bug */ /* BDF of pcie host 8 -> stream ID of pcie ITS */ [0004] Input base : 0000BA00 [0004] ID Count : 00000100 // the number of IDs in range diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl index 63d11b83ebed..c9e1cbd6830d 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl @@ -36,10 +36,10 @@ /*0x4c RC 0 */ [0001] Type : 02 [0002] Length : 00A0 -[0001] Revision : 00 +[0001] Revision : 01 [0004] Reserved : 00000000 [0004] Mapping Count : 0000000C -[0004] Mapping Offset : 00000028 +[0004] Mapping Offset : 00000024 [0008] Memory Properties : [IORT Memory Access Properties] [0004] Cache Coherency : 00000001 @@ -54,6 +54,8 @@ Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000000 // should match with above MCFG + Memory Size Limit : 00 + Reserved : 00000000 /* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */ [0004] Input base : 00000000