From patchwork Thu Feb 28 04:49:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 15131 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8AE3023E24 for ; Thu, 28 Feb 2013 04:50:37 +0000 (UTC) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by fiordland.canonical.com (Postfix) with ESMTP id 35D96A18B22 for ; Thu, 28 Feb 2013 04:50:37 +0000 (UTC) Received: by mail-ve0-f175.google.com with SMTP id cy12so1388930veb.34 for ; Wed, 27 Feb 2013 20:50:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=/PgQ3eBYFhlrFAhpWsXicQj14Ku4C9dqd637hZTkwPg=; b=NR3J/9QEQ78re8Mi2oTjt6sVJp5BMcirINLmq5YMgPpUr0hf2WoRFWKPEakCc2ighN FuokXYLRe6Ao/8ITjd5Fj0UK/W0noP/iPYF34TUjZCq0f4zlI+t/2tG9/ubRzfEHVfsK 0k+obCbmK3wwZNsCmtHkH+0FfDvfHr/4jsEOW75a7qkxNE0YUYeUa9EPcoyv8GAPbd2Q LnwQAR3/6ZthzPEy2iSuoMBjqW4xJoDjuaekeVYKcJ5sAU8r7RmkgZGM9P8YZKqbHBzD es0lqYnSfir2nN/TR2WI68gd7LxgKXx1zCA3NjX0FHGtJaJQW66RtzMSBCCWml5xj0bE Rcsg== X-Received: by 10.52.18.148 with SMTP id w20mr1747921vdd.8.1362027036685; Wed, 27 Feb 2013 20:50:36 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp206256veb; Wed, 27 Feb 2013 20:50:36 -0800 (PST) X-Received: by 10.66.216.231 with SMTP id ot7mr11198673pac.173.1362027035517; Wed, 27 Feb 2013 20:50:35 -0800 (PST) Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by mx.google.com with ESMTPS id b7si7518596paz.245.2013.02.27.20.50.35 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 20:50:35 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.49 is neither permitted nor denied by best guess record for domain of mturquette@linaro.org) client-ip=209.85.220.49; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.49 is neither permitted nor denied by best guess record for domain of mturquette@linaro.org) smtp.mail=mturquette@linaro.org Received: by mail-pa0-f49.google.com with SMTP id kp6so894178pab.36 for ; Wed, 27 Feb 2013 20:50:35 -0800 (PST) X-Received: by 10.68.227.9 with SMTP id rw9mr7152211pbc.185.1362027035152; Wed, 27 Feb 2013 20:50:35 -0800 (PST) Received: from quantum.gateway.2wire.net (adsl-69-228-86-207.dsl.pltn13.pacbell.net. [69.228.86.207]) by mx.google.com with ESMTPS id y9sm7799811paw.1.2013.02.27.20.50.29 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 20:50:34 -0800 (PST) From: Mike Turquette To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-dev@lists.linaro.org, Mike Turquette Subject: [PATCH 5/5] HACK: omap: opp: add fake 400MHz OPP to bypass MPU Date: Wed, 27 Feb 2013 20:49:29 -0800 Message-Id: <1362026969-11457-6-git-send-email-mturquette@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362026969-11457-1-git-send-email-mturquette@linaro.org> References: <1362026969-11457-1-git-send-email-mturquette@linaro.org> X-Gm-Message-State: ALoCoQlqKlKb8yJ8lpKKVrHyvJMpDXSqsYlQ7Sh+eMGvkjfpKUzcXII4hjtao86ycORrzpQKDuqX From: Mike Turquette The following is another silly patch which was done to test calling clk_set_parent from within a call to clk_set_rate. It may make your board burst into flames or otherwise void various warrantees. This patch introduces a 400MHz OPP for the MPU, which happens to correspond to the bypass clk rate on the 4430 Panda board and 4460 Panda ES board, both using a 38.4MHz SYS_CLK oscillator rate. One may test this by using the cpufreq-userspace governor and executing: echo 400000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed On Panda ES validation can be done via: $ find /debug/clk/ -iname "dpll_mpu_ck" /debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck $ echo 400000 > scaling_setspeed $ find /debug/clk/ -iname "dpll_mpu_ck" /debug/clk/virt_38400000_ck/sys_clkin_ck/dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk/dpll_mpu_ck $ cat /proc/cpuinfo ... BogoMIPS : 794.26 ... $ cat /sys/class/regulator/regulator.3/microvolts 1200000 Not-signed-off-by: Mike Turquette --- arch/arm/mach-omap2/opp4xxx_data.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index d470b72..c7bccf7 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -67,6 +67,15 @@ struct omap_volt_data omap443x_vdd_core_volt_data[] = { static struct omap_opp_def __initdata omap443x_opp_def_list[] = { /* MPU OPP1 - OPP50 */ OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV), + /* + * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI + * + * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE. After + * transitioning to this OPP you can see the migration in debugfs: + * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to + * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk + */ + OPP_INITIALIZER("mpu", true, 400000000, 1100000), /* MPU OPP2 - OPP100 */ OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV), /* MPU OPP3 - OPP-Turbo */ @@ -126,6 +135,15 @@ struct omap_volt_data omap446x_vdd_core_volt_data[] = { static struct omap_opp_def __initdata omap446x_opp_def_list[] = { /* MPU OPP1 - OPP50 */ OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV), + /* + * MPU OPP1.5 - 400MHz - completely FAKE - not endorsed by TI + * + * DPLL_MPU is in Low Power Bypass driven by DPLL_CORE. After + * transitioning to this OPP you can see the migration in debugfs: + * /d/clk/virt_38400000_ck/sys_clkin_ck/dpll_mpu_ck to + * /d/.../dpll_core_ck/dpll_core_x2_ck/dpll_core_m5x2_ck/div_mpu_hs_clk + */ + OPP_INITIALIZER("mpu", true, 400000000, 1100000), /* MPU OPP2 - OPP100 */ OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV), /* MPU OPP3 - OPP-Turbo */