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[209.132.180.67]) by mx.google.com with ESMTP id h3si30324744pgi.391.2018.11.16.02.05.08; Fri, 16 Nov 2018 02:05:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EYgZ6R/G"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389569AbeKPUQo (ORCPT + 32 others); Fri, 16 Nov 2018 15:16:44 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46473 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389547AbeKPUQn (ORCPT ); Fri, 16 Nov 2018 15:16:43 -0500 Received: by mail-pg1-f193.google.com with SMTP id w7so10386910pgp.13 for ; Fri, 16 Nov 2018 02:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HClVvGiwOuWgQ6TjJ14HNKIrS62CNCv2+c1OlYODQLQ=; b=EYgZ6R/GukaNgdoqsL+uxEcbK4u50GApx9Jrvrdq5PtjcvbOzdKihSLY8qHyk4JUah JmTUeiVCXXf0NaYEjIQgSxfEqzMrhj2guSYLHqQs7ijcz+wlMZZbhmO5xNnUky32xYNo fr7LO3IgRE/Gm4kOImnuv0ghPrZqulGfKR3WI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HClVvGiwOuWgQ6TjJ14HNKIrS62CNCv2+c1OlYODQLQ=; b=X/9JP9Q6PdzILX9P/uOIZBqkL+aq9nfZfzBrWcqQHOwqZMW4gd4CA2smbIv2gM/UY5 3WHtYTFTMuxUfECy3lD1ZagW45govbl0cqLJEJX+8vFGtDmrPWdRFqIxx+bW9AjYxSIv HVSe4a7i342gP4FEl52i8Ixa7Aap5RX8TgVpvkXNm/RzwNhURe5rtIrfphB9w9mKUOBA w9maKwJiSRXKiKgNB2ZIyj5rI+oFHHBxrkf2+AQAqAN0+wW9ZP7keCac148+J3cxU7M3 mWeb3+bUCcInR8jvJjxTfTxk/tzSjp36Ubuz8b4HVbDDsIfly40+reWzI6PsVKw3mL1o ZrvA== X-Gm-Message-State: AGRZ1gK2pEPpgRFSodPk6BPFCVRR/Gu0+OH38YoyXzJCbuJqhnhv1jI+ qghvd5fLGttATFrZykpmhtaU9A== X-Received: by 2002:a63:9a52:: with SMTP id e18mr9300065pgo.14.1542362705320; Fri, 16 Nov 2018 02:05:05 -0800 (PST) Received: from localhost ([122.172.88.116]) by smtp.gmail.com with ESMTPSA id y9-v6sm32421519pfe.152.2018.11.16.02.05.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 02:05:04 -0800 (PST) From: Viresh Kumar To: Mark Rutland , Rob Herring , arm@kernel.org, Wei Xu Cc: Viresh Kumar , devicetree@vger.kernel.org, Vincent Guittot , Daniel Lezcano , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/10] arm64: dts: hi3660: Add missing cooling device properties for CPUs Date: Fri, 16 Nov 2018 15:34:27 +0530 Message-Id: <042e5e647a7b54f4322024f1b3e286b6b6d69175.1542362530.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.19.1.568.g152ad8e3369a In-Reply-To: References: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.19.1.568.g152ad8e3369a diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f432b0a88c65..d943a96eedee 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -79,6 +79,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -91,6 +92,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -103,6 +105,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu4: cpu@100 { @@ -129,6 +132,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; cpu6: cpu@102 { @@ -141,6 +145,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; cpu7: cpu@103 { @@ -153,6 +158,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; idle-states {