From patchwork Fri Nov 16 10:39:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151328 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp262194ljp; Fri, 16 Nov 2018 02:42:43 -0800 (PST) X-Google-Smtp-Source: AFSGD/WKDMHjqXeQPId5ldopwVr5dxXhr/75sc+XBkBgPCpa8Ryx7SAMM5t1GL8DO7/qrNrailkd X-Received: by 2002:a50:9624:: with SMTP id y33mr64841eda.206.1542364963700; Fri, 16 Nov 2018 02:42:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542364963; cv=none; d=google.com; s=arc-20160816; b=FWoUEhBIEgaBYV8gph5OvO0LVonePFaNJfrZyl5qOKjjwlZaoh6lBeOrF22wI+uhzB GTsO8m0mReDz7HlH8/1MK3cZ8wEPoiceKwiJdJguVXZJo/eYPM3ldqYnGWSbVXbqRamW FuuaBGCOVyWZXssP238lnJYgqD5BaHRdI6afNGTHopMqX3SBRIHzlzlcrxH1rB+GLrkR jKP2rHItJdLFWi/aqJqF6kflMmMyvS4/R8FPhJ0VpqM9D/aDaN/TuKa112+SgoGwA6Xb 9RiFlSfs9tGWtJnFyW2qTTqim2xuO7ruFqt7kRoqgblns8GTecvyAR8H63bNIVuBvGXs gr2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature; bh=lOMoY3gq5YPKZtwMLOqXgdeJ3l++0tJd8LOg1dN2PVg=; b=p38h6PYmIDSCeYBU5wDblgzdZBgOH+Pg1HaUPFht82zLg48CpMk7m4zDELNiADuWGU 80gBuGisEsw0saOOYhaA63rprsFHiDNxqXToAwe4GyMUwktI5In27tPSZYiYx/C8LPK8 hnAFbMhVGGUxyk6F3/XqCH/jZAHW2EcTS6cfqfyiehULlnPFKns23/TGvoUki1M7eTai 21t6NJQJ4C7JIGTlwiIUwToctFbYtMtVbOe+hjoAGO312lN61p8bEJImrBGO7ZqlC58T JUVeEkWLFoirXif+oSKqIHxUa+I5Um6dyHtKKSNK/SoNwYGtuqVImmo55QG5aFDJSt0j svDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NsahAsGR; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id f10si9525370edb.244.2018.11.16.02.42.43; Fri, 16 Nov 2018 02:42:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NsahAsGR; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 405FFC224ED; Fri, 16 Nov 2018 10:41:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BC3BCC224D2; Fri, 16 Nov 2018 10:40:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E2259C224D5; Fri, 16 Nov 2018 10:40:09 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id 4F6CEC224D9 for ; Fri, 16 Nov 2018 10:40:06 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id r11-v6so21532597wmb.2 for ; Fri, 16 Nov 2018 02:40:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ejct8UX6bJFOwwcKpqlnsgVAZ2Zlsuz1xmZoHn47dBQ=; b=NsahAsGRjo1OO8o/0wmThvd3BZUY9n2dpwd08qdFZDkxv3Kh3NvXQ/+2zdW6JxyA/s lAeVKwyZZi1Ic2wdb0G8rOVxnHZwc2GoI8GTLMsmpjNN+pi+1M8BKZOK/o8LiRcCrL8e oqm789fT5d3U8/VpfUFlvmcC8mrHoQSWFguFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ejct8UX6bJFOwwcKpqlnsgVAZ2Zlsuz1xmZoHn47dBQ=; b=kOS2Jnr8DTqwxN5tVSJPEwRZuFNbIT5UAm5MD5ujjE7iXSnhMqWtlefQ8nHCgRtnuZ ndf9zO4toqaW+6glAGukgZG2pOoLNxRIc550bghkzGlnT0fVvsO3N2OjYmGBv8YUOQEW ci94+r40i9p0+0QaMlNwvFY4vBamHczztqZmz0KQU2Usiu1YWaMP2Wrj/CyDQdbgzJ6F EmbJTDrsvN8bs1rn3d3WJh6LJsg7OVP2Nh1Z2RlubxxPhlYk7lyDcPp9+Bbsr3q7quDb mgyACC0JJ9n7sAdWcFeEJ9tQAOb24oh4tblBpUAaatjjwiBhp2rWqNh/mamC8/H8Psxu gAJw== X-Gm-Message-State: AGRZ1gKCYlSBVkUBgnlwSMsMiV4O/iHxWYTU0x2X0vRCThhoVoIyeyak JpLf6OGSJGPc5O2+x+Hu8atD6Q== X-Received: by 2002:a1c:410b:: with SMTP id o11mr2107205wma.109.1542364805936; Fri, 16 Nov 2018 02:40:05 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105d:3df6:606e:fa38:9819:9c69]) by smtp.gmail.com with ESMTPSA id f68sm13960857wmd.15.2018.11.16.02.40.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Nov 2018 02:40:05 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Fri, 16 Nov 2018 11:39:47 +0100 Message-Id: <20181116103947.11002-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181116103947.11002-1-benjamin.gaignard@st.com> References: <20181116103947.11002-1-benjamin.gaignard@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 4/4] pinctrl: stm32: make pinctrl use hwspinlock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Benjamin Gaignard Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-ed1.dts | 4 ++++ drivers/pinctrl/pinctrl_stm32.c | 27 +++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index fc277dd7d2..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -369,6 +369,10 @@ status = "okay"; }; +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 31285cdd57..402b7803fc 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -19,12 +20,20 @@ static int stm32_gpio_config(struct gpio_desc *desc, { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct hwspinlock *hws = dev_get_priv(dev_get_parent(desc->dev)); u32 index; + int ret; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ret = hwspinlock_lock_timeout(hws, 1); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -39,6 +48,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(hws); + return 0; } @@ -176,6 +187,20 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, } #endif /* PINCTRL_FULL */ +static int stm32_pinctrl_probe(struct udevice *dev) +{ + struct hwspinlock *hws = dev_get_priv(dev); + int err; + + /* hwspinlock property is optional, just log the error */ + err = hwspinlock_get_by_index(dev, 0, hws); + if (err) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, err); + + return 0; +} + static struct pinctrl_ops stm32_pinctrl_ops = { #if CONFIG_IS_ENABLED(PINCTRL_FULL) .set_state = stm32_pinctrl_set_state, @@ -200,4 +225,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, .bind = dm_scan_fdt_dev, + .probe = stm32_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct hwspinlock), };