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[209.132.180.67]) by mx.google.com with ESMTP id v5si3188806plg.318.2018.11.20.19.38.33; Tue, 20 Nov 2018 19:38:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ldy/r4Cy"; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725995AbeKUOLG (ORCPT + 2 others); Wed, 21 Nov 2018 09:11:06 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:43071 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727175AbeKUOLG (ORCPT ); Wed, 21 Nov 2018 09:11:06 -0500 Received: by mail-pl1-f194.google.com with SMTP id gn14so3382340plb.10 for ; Tue, 20 Nov 2018 19:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Z5MAsdKFcai4UXx4/yK6UISTrk8OVTQoys01PtcxnI=; b=Ldy/r4CyLlqWiQEOQe40jvqOZsrTRgEo5fCiXYU6f1kvPoRcFFBCfkjeXAHf52ENq2 J+uw/WoUCDJUaqr60w5UpLkN6dMqCqSmPpygRSU+nAhMHOJqH78WyMlWBaAYIUD3p0K6 qvuMYsNRFCdbkd52Q6RA8Am5qgy+j8+SccCps= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Z5MAsdKFcai4UXx4/yK6UISTrk8OVTQoys01PtcxnI=; b=WL26UAr+99rtEEGaia1lyWID7mcfhMbMouUhrzacCdyN6EQhyTvTiG+3sJy+ffg4bO H2AB8PdjqV1XfAwf/4xKBst/NIHlvdZIXNOI2UgHqL0TV04bfO61yVnfEUZULvOhMhUO CAEZPtEEgHpa8Ryhxm234TVclD0+nck95jRBOKeUCFatUXTtkTM81Xmk9t/7f1glQj56 oxQ2bHK/G7CRnXk1pQf0lYLeeK/WHa/WcSDRrrVm8v49JhPeJpg39SkaeYKvap9CBMTg +uy59xMfkk/YePElorolpd8VnVwxSc+oDbPJgJ/zHaZlf4SrnqZOdgyHcgZLq9dairc9 QIkA== X-Gm-Message-State: AA+aEWY7e7oJpzEwbAWtuO7hIUVg2Y/OHa898Owlz1KBZ55vdLRAHXfX Z97nOh9E2m6W5fyJgMuU84Wk X-Received: by 2002:a17:902:3341:: with SMTP id a59-v6mr4986711plc.220.1542771511789; Tue, 20 Nov 2018 19:38:31 -0800 (PST) Received: from localhost.localdomain ([2409:4072:98b:9501:106a:f751:df0d:9e68]) by smtp.gmail.com with ESMTPSA id z8sm72025095pgz.53.2018.11.20.19.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 19:38:31 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, robh+dt@kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, daniel.lezcano@linaro.org, gregkh@linuxfoundation.org, jslaby@suse.com Cc: afaerber@suse.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, overseas.sales@unisoc.com, Manivannan Sadhasivam Subject: [PATCH v2 08/15] irqchip: Add RDA8810PL interrupt driver Date: Wed, 21 Nov 2018 09:06:45 +0530 Message-Id: <20181121033652.12247-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121033652.12247-1-manivannan.sadhasivam@linaro.org> References: <20181121033652.12247-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add interrupt driver for RDA Micro RDA8810PL SoC. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam --- arch/arm/mach-rda/Kconfig | 1 + drivers/irqchip/Kconfig | 4 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rda-intc.c | 113 +++++++++++++++++++++++++++++++++ 4 files changed, 119 insertions(+) create mode 100644 drivers/irqchip/irq-rda-intc.c -- 2.17.1 diff --git a/arch/arm/mach-rda/Kconfig b/arch/arm/mach-rda/Kconfig index dafab78d7aab..29012bc68ca4 100644 --- a/arch/arm/mach-rda/Kconfig +++ b/arch/arm/mach-rda/Kconfig @@ -3,5 +3,6 @@ menuconfig ARCH_RDA depends on ARCH_MULTI_V7 select COMMON_CLK select GENERIC_IRQ_CHIP + select RDA_INTC help This enables support for the RDA Micro 8810PL SoC family. diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 51a5ef0e96ed..9d54645870ad 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -195,6 +195,10 @@ config JCORE_AIC help Support for the J-Core integrated AIC. +config RDA_INTC + bool + select IRQ_DOMAIN + config RENESAS_INTC_IRQPIN bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 794c13d3ac3d..417108027e40 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o +obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/drivers/irqchip/irq-rda-intc.c b/drivers/irqchip/irq-rda-intc.c new file mode 100644 index 000000000000..1b372bdb23bc --- /dev/null +++ b/drivers/irqchip/irq-rda-intc.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RDA8810PL SoC irqchip driver + * + * Copyright RDA Microelectronics Company Limited + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define RDA_INTC_FINALSTATUS 0x00 +#define RDA_INTC_STATUS 0x04 +#define RDA_INTC_MASK_SET 0x08 +#define RDA_INTC_MASK_CLR 0x0c +#define RDA_INTC_WAKEUP_MASK 0x18 +#define RDA_INTC_CPU_SLEEP 0x1c + +#define RDA_IRQ_MASK_ALL 0xFFFFFFFF + +#define RDA_NR_IRQS 32 + +static void __iomem *base; + +static void rda_intc_mask_irq(struct irq_data *d) +{ + writel_relaxed(BIT(d->hwirq), base + RDA_INTC_MASK_CLR); +} + +static void rda_intc_unmask_irq(struct irq_data *d) +{ + writel_relaxed(BIT(d->hwirq), base + RDA_INTC_MASK_SET); +} + +static int rda_intc_set_type(struct irq_data *data, unsigned int flow_type) +{ + /* Hardware supports only level triggered interrupts */ + if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) + irq_set_handler(data->irq, handle_level_irq); + else + return -EINVAL; + + return 0; +} + +static struct irq_domain *rda_irq_domain; + +static void __exception_irq_entry rda_handle_irq(struct pt_regs *regs) +{ + u32 stat = readl_relaxed(base + RDA_INTC_FINALSTATUS); + u32 hwirq; + + while (stat) { + hwirq = __fls(stat); + handle_domain_irq(rda_irq_domain, hwirq, regs); + stat &= ~(1 << hwirq); + } +} + +static struct irq_chip rda_irq_chip = { + .name = "rda-intc", + .irq_mask = rda_intc_mask_irq, + .irq_unmask = rda_intc_unmask_irq, + .irq_set_type = rda_intc_set_type, +}; + +static int rda_irq_map(struct irq_domain *d, + unsigned int virq, irq_hw_number_t hw) +{ + irq_set_status_flags(virq, IRQ_LEVEL); + irq_set_chip_and_handler(virq, &rda_irq_chip, handle_level_irq); + irq_set_chip_data(virq, d->host_data); + irq_set_probe(virq); + + return 0; +} + +static const struct irq_domain_ops rda_irq_domain_ops = { + .map = rda_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init rda8810_intc_init(struct device_node *node, + struct device_node *parent) +{ + base = of_io_request_and_map(node, 0, "rda-intc"); + if (!base) + return -ENXIO; + + /* Mask, and invalidate all interrupt sources */ + writel_relaxed(RDA_IRQ_MASK_ALL, base + RDA_INTC_MASK_CLR); + + rda_irq_domain = irq_domain_create_linear(&node->fwnode, RDA_NR_IRQS, + &rda_irq_domain_ops, base); + if (WARN_ON(!rda_irq_domain)) { + iounmap(base); + return -ENODEV; + } + + set_handle_irq(rda_handle_irq); + + return 0; +} + +IRQCHIP_DECLARE(rda_intc, "rda,8810pl-intc", rda8810_intc_init);