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[198.145.21.10]) by mx.google.com with ESMTPS id b3si1638772pgc.587.2018.11.26.14.38.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Nov 2018 14:38:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PVkigk1r; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 526E421195BC6; Mon, 26 Nov 2018 14:38:30 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BFF0A21B02822 for ; Mon, 26 Nov 2018 14:38:28 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id j207so12811566wmj.1 for ; Mon, 26 Nov 2018 14:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aYnHk1FahDlTiadS/Wd3xqjc/XFbp1D+Z5OcvD3RCRQ=; b=PVkigk1rwGoQ9BiUfDbtjuW7yN+CI+fCtVzlh2kv0kH/Jcy7ENgKOzAPMJaGAI0MIp H3uvZ0eqqc9+2iOqOjpmSjuiseRbUmSzXYZHNr5TeazzRKQ7dDjpPagvuWadyLkXMyrl K0FE4A/vVir0Q/wnQrXuC8N99Be81TFrxTnMA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aYnHk1FahDlTiadS/Wd3xqjc/XFbp1D+Z5OcvD3RCRQ=; b=unEzYXU2wzGUxUgOQMrM98zSNgPbsgYI8/SAP7tGO11WyUml0e2FHaBQq4DSeedY9u vanM1hQcLN3VxuNEAPeXgTGBjN+JkZp5Zc9pkW1uOmxAKOMh22DK174X4GMYXyy578Ys MahA4OnPIstxc0CBfxUpM+BmJSvaFBdg/aW+kAw69ZhwsuPI0Eb05VRyy/uUR3uxJvEM 9LrFM6N+/tIfink7/vPwnOxdmxdhQ8HRbQSwuI8Z8Nw+e44BrV8g+tbuQ5ugwiUW8ii+ Hr+Q7ExXLvXC4V/VOxbgDCZsrgCoBtE6GHc9nFE085H8ZdwIu4Is8kjyu70Px5Tg4HcG ImlA== X-Gm-Message-State: AA+aEWbejSqCybBjacC0R7uozbBGLg544AuPngpdNfAafoKWNcMJ3O4Y 3hR6zGDTc+6FEQotYC3X9ZkMxW+NREk= X-Received: by 2002:a1c:8484:: with SMTP id g126mr14028797wmd.117.1543271906932; Mon, 26 Nov 2018 14:38:26 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8571:4c23:4f5c:5eb7]) by smtp.gmail.com with ESMTPSA id v5sm2641916wrn.71.2018.11.26.14.38.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Nov 2018 14:38:25 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 26 Nov 2018 23:37:49 +0100 Message-Id: <20181126223801.17121-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181126223801.17121-1-ard.biesheuvel@linaro.org> References: <20181126223801.17121-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 01/13] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Laszlo Ersek , Eric Auger Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 17 +++++++++++++++++ ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ 3 files changed, 41 insertions(+) -- 2.19.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Philippe Mathieu-Daudé diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index ffda50e9d767..b22879fe6e94 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -29,6 +29,17 @@ #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ EFI_MEMORY_WT | EFI_MEMORY_WB | \ EFI_MEMORY_UCE) +// +// ARM_MMU_IDMAP_RANGE defines the maximum size of the identity mapping +// that covers the entire address space when running in UEFI. This is +// limited to what can architecturally be mapped using a 4 KB granule, +// even if the hardware is capable of mapping more using larger pages. +// +#ifdef MDE_CPU_ARM +#define ARM_MMU_IDMAP_RANGE (1ULL << 32) +#else +#define ARM_MMU_IDMAP_RANGE (1ULL << 48) +#endif /** * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. @@ -733,4 +744,10 @@ ArmWriteCntvOff ( UINT64 Val ); +UINTN +EFIAPI +ArmGetPhysicalAddressBits ( + VOID + ); + #endif // __ARM_LIB__ diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index 1ef2f61f5979..7332601241aa 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) 3:msr sctlr_el3, x0 4:ret +ASM_FUNC(ArmGetPhysicalAddressBits) + mrs x0, id_aa64mmfr0_el1 + adr x1, .LPARanges + and x0, x0, #7 + ldrb w0, [x1, x0] + ret + +// +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the +// physical address space support on this CPU: +// 0 == 32 bits, 1 == 36 bits, etc etc +// 6 and 7 are reserved +// +.LPARanges: + .byte 32, 36, 40, 42, 44, 48, 52, -1 + ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index f2a517671f0a..f2f3c9a25991 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) isb bx lr +ASM_FUNC (ArmGetPhysicalAddressBits) + mrc p15, 0, r0, c0, c1, 4 // MMFR0 + and r0, r0, #0xf // VMSA [3:0] + cmp r0, #5 // >5 implies LPAE support + movlt r0, #32 // 32 bits if no LPAE + movge r0, #40 // 40 bits if LPAE + bx lr + ASM_FUNCTION_REMOVE_IF_UNREFERENCED