[v3] drm/panel: Set max rate for Ilitek ILI9881C

Message ID 20181127134057.15659-1-linus.walleij@linaro.org
State New
Headers show
Series
  • [v3] drm/panel: Set max rate for Ilitek ILI9881C
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Commit Message

Linus Walleij Nov. 27, 2018, 1:40 p.m.
After adding the hs_rate and lp_rate fields to the DSI device
we need to populate these accordingly so display drivers can
respect them.

This figure for HS rate comes from the ILI9881C manual, the
calculation is explained in the comment.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLov v2->v3:
- Fix up the HS speed to 275 MHz, as the speed is double
  data rate.
ChangeLog v1->v2:
- Add LP speed after Andrzej's observation.
- Collect Maxime's ACK (hope it's fine also with the LP speed)
---
 drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Thierry Reding Nov. 27, 2018, 2:18 p.m. | #1
On Tue, Nov 27, 2018 at 02:40:57PM +0100, Linus Walleij wrote:
> After adding the hs_rate and lp_rate fields to the DSI device

> we need to populate these accordingly so display drivers can

> respect them.

> 

> This figure for HS rate comes from the ILI9881C manual, the

> calculation is explained in the comment.

> 

> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>

> Cc: Andrzej Hajda <a.hajda@samsung.com>

> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

> ---

> ChangeLov v2->v3:

> - Fix up the HS speed to 275 MHz, as the speed is double

>   data rate.

> ChangeLog v1->v2:

> - Add LP speed after Andrzej's observation.

> - Collect Maxime's ACK (hope it's fine also with the LP speed)

> ---

>  drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 15 +++++++++++++++

>  1 file changed, 15 insertions(+)


Acked-by: Thierry Reding <treding@nvidia.com>
Andrzej Hajda Nov. 29, 2018, 9:28 a.m. | #2
On 27.11.2018 14:40, Linus Walleij wrote:
> After adding the hs_rate and lp_rate fields to the DSI device
> we need to populate these accordingly so display drivers can
> respect them.
>
> This figure for HS rate comes from the ILI9881C manual, the
> calculation is explained in the comment.
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Andrzej Hajda <a.hajda@samsung.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLov v2->v3:
> - Fix up the HS speed to 275 MHz, as the speed is double
>   data rate.
> ChangeLog v1->v2:
> - Add LP speed after Andrzej's observation.
> - Collect Maxime's ACK (hope it's fine also with the LP speed)
> ---
>  drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
> index 3ad4a46c4e94..8c00193c2400 100644
> --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
> +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
> @@ -465,6 +465,21 @@ static int ili9881c_dsi_probe(struct mipi_dsi_device *dsi)
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->lanes = 4;
> +	/*
> +	 * The datasheet (table 39) specifies "limited clock channel speed"
> +	 * for 4 lanes as 550 Mbps per lane for RGB888. As this is 4 bits at
> +	 * the time,


I don't understand the part "As this is 4 bits at the time" ? Where it
came from?

I guess the only calculation should be due to double-data-rate:

hs_rate = 550Mbps / 2BitsPerTick


>  at double data rate the maximum HS frequency should
> +	 * be:
> +	 * 550/4 * 2 = 275 MHz.
> +	 */
> +	dsi->hs_rate = 275000000;
> +	/*
> +	 * Table 42 says: "Length of LP-00, LP-01, LP-10 or LP-11 periods":
> +	 * min 50ns, max 75ns. 1/50ns = max LPM rate = 20.000.000Hz.
> +	 * Since LP transmissions are to periods per bit, this should be


Again:

s/to/two/


Regards

Andrzej


> +	 * 10 MHz.
> +	 */
> +	dsi->lp_rate = 10000000;
>  
>  	return mipi_dsi_attach(dsi);
>  }

Patch

diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
index 3ad4a46c4e94..8c00193c2400 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
@@ -465,6 +465,21 @@  static int ili9881c_dsi_probe(struct mipi_dsi_device *dsi)
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->lanes = 4;
+	/*
+	 * The datasheet (table 39) specifies "limited clock channel speed"
+	 * for 4 lanes as 550 Mbps per lane for RGB888. As this is 4 bits at
+	 * the time, at double data rate the maximum HS frequency should
+	 * be:
+	 * 550/4 * 2 = 275 MHz.
+	 */
+	dsi->hs_rate = 275000000;
+	/*
+	 * Table 42 says: "Length of LP-00, LP-01, LP-10 or LP-11 periods":
+	 * min 50ns, max 75ns. 1/50ns = max LPM rate = 20.000.000Hz.
+	 * Since LP transmissions are to periods per bit, this should be
+	 * 10 MHz.
+	 */
+	dsi->lp_rate = 10000000;
 
 	return mipi_dsi_attach(dsi);
 }