From patchwork Thu Nov 29 17:47:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 152451 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2672788ljp; Thu, 29 Nov 2018 09:47:58 -0800 (PST) X-Received: by 2002:a19:c954:: with SMTP id z81mr1602667lff.150.1543513678100; Thu, 29 Nov 2018 09:47:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543513678; cv=none; d=google.com; s=arc-20160816; b=djKqGE2rQ7Ls5CO7hh03JI6eLYVY74vCXktqx2OjP8b1IwnEZr81uQUuMxT+dFAF9U cSrCbDuhDnNHfQlwwbsvL3h7wPau5yAAsoTRdB37gFy/dYIVmMXOgUcFh2JhGRx2z3H2 3j1QyjdZPZKfGs5i5zpveq9ZRqttO7g5r7QKsemC+Wg9XDoFHKVsHD6U+DNsY0aedOTs T/xQA4iCARjp35rvRbcJv1Bak5dbATR0Q9JdOFR6Zy6YMheXaFJG1OmILB7sj8ml3GBx 1I4oK3pXYDegzNlW9BnL99SKXWDLo/gjmLIGJk/CpI6MJQzy7acbdw1OKnC5FphgMaZZ CEFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=edUuds9oK7rq3a7y1o1twsgnSy+L5oYmA4xb9WHJ9+k=; b=VLlfXytcVC+L5Epf4rezsDW7cijJxxgV6pLrDg/ZltSdZ0iLkBNar/nN1tOiMoEoHh VLtE3jr/b90OzjXrxq0jvtqOa9ckKavuz7Pi6EeHhuIuh80a86ESIFdZTC7TZ4nHVN4X i7dGFAXck7WhBQtza2L/TIklV3e8MPrm6vXR4KDrWmsxK/uxE3xZSX4JukkDumffXRlI sWbe83O3wANjvjCHCpjksqmenZkXOpuy57Qm1UGTFih4wwDbJl3gAzRDYK7AZIp1m2H9 14GAv1SlmeLtlx5fjBfn/hnYRp+UtZ3vB5NHRt6M+S9jgSszQtQzUbAMHigwJrIZfghM 1D/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A6wx/B1l"; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id 17sor799675lfb.4.2018.11.29.09.47.58 for (Google Transport Security); Thu, 29 Nov 2018 09:47:58 -0800 (PST) Received-SPF: pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A6wx/B1l"; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=edUuds9oK7rq3a7y1o1twsgnSy+L5oYmA4xb9WHJ9+k=; b=A6wx/B1lx1+bygG6vNTP5U1cnmX9jGEyu1b3aHBxjvlAIzHP/jh/FWsauGN28VCUzQ ljorwL5unf+YDLuCY0t6Ivi4w5Lj71gYb0YXCgZ4jRGr+Jt6dYLG2khG3OERWdIZ5xkY Ac65FBUbc5jI8f4Eyk6HdNONOTEhIVUNeWVhQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=edUuds9oK7rq3a7y1o1twsgnSy+L5oYmA4xb9WHJ9+k=; b=sLNg9bPITjnx6QdBKiDNDXmgV2mhOZt6UEOBGk7TZkGl2+fbYr9TDPUwnnegEK7sCj vi0uB02/0j/56aKZCyoyeguTkItudxLxAg/Pmf2FvOUmsOg6LfIyaq+LUskgdHnj6BsN HY+VU3HsFijG/bqjaa0n3pepRdp/N1qNiAGClmh689BgJ0S9RozdBtnYPoP2bgIbDFAd 9z4gn/JYniTVdX9DzZFeuj60MD8VR52yiQw45mXRUgv4L7g1qOGPckiN+g1QQgN2Ivbe wlCy8IZf5fTwTh3P8qh0Uxyoi+o4WyGJvBeJJyLdzinM+JSN0V4WAHfu6gYxPW4XY3s3 2nfQ== X-Gm-Message-State: AA+aEWYv0NMzb82rHN0pE7dX4NOiMHou9LhMwO48uG97X80c1GNMs9Ek fLp0+IpdcH3Wx0gZUWVuirpbKZb/ X-Google-Smtp-Source: AFSGD/XVzFGUZimGhzy88XMVy4uhorvpa7/8oAxi7Md22GA4kR2vIjSPoAiN4QAPlVeK/uqUb9G+/Q== X-Received: by 2002:a19:59c2:: with SMTP id n185mr1558629lfb.118.1543513677002; Thu, 29 Nov 2018 09:47:57 -0800 (PST) Return-Path: Received: from localhost.localdomain (h-158-174-22-210.NA.cust.bahnhof.se. [158.174.22.210]) by smtp.gmail.com with ESMTPSA id j76-v6sm393983ljb.12.2018.11.29.09.47.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 09:47:56 -0800 (PST) From: Ulf Hansson To: "Rafael J . Wysocki" , Sudeep Holla , Lorenzo Pieralisi , Mark Rutland , Daniel Lezcano , linux-pm@vger.kernel.org Cc: "Raju P . L . S . S . S . N" , Stephen Boyd , Tony Lindgren , Kevin Hilman , Lina Iyer , Ulf Hansson , Viresh Kumar , Vincent Guittot , Geert Uytterhoeven , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 27/27] arm64: dts: hikey: Convert to the hierarchical CPU topology layout Date: Thu, 29 Nov 2018 18:47:00 +0100 Message-Id: <20181129174700.16585-28-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181129174700.16585-1-ulf.hansson@linaro.org> References: <20181129174700.16585-1-ulf.hansson@linaro.org> To enable the OS to manage last-man standing activities for a CPU, while an idle state for a group of CPUs is selected, let's convert the Hikey platform into using the hierarchical CPU topology layout. Signed-off-by: Ulf Hansson --- Changes in v10: - New patch. --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 87 ++++++++++++++++++++--- 1 file changed, 76 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 97d5bf2c6ec5..fa5b385cfbc4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -20,6 +20,64 @@ psci { compatible = "arm,psci-0.2"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD0>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD1>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD0: cluster-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; + + CLUSTER_PD1: cluster-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; cpus { @@ -70,9 +128,8 @@ }; CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000000>; entry-latency-us = <1000>; exit-latency-us = <700>; min-residency-us = <2700>; @@ -88,9 +145,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; cpu1: cpu@1 { @@ -101,9 +159,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; cpu2: cpu@2 { @@ -114,9 +173,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; cpu3: cpu@3 { @@ -127,9 +187,10 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu4: cpu@100 { @@ -140,9 +201,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; }; cpu5: cpu@101 { @@ -153,9 +215,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; }; cpu6: cpu@102 { @@ -166,9 +229,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; }; cpu7: cpu@103 { @@ -179,9 +243,10 @@ next-level-cache = <&CLUSTER1_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; }; CLUSTER0_L2: l2-cache0 {