From patchwork Mon Dec 3 17:16:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 152716 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7060912ljp; Mon, 3 Dec 2018 09:17:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/Wog/YP/0czNL9m1xSpix+qJtz2P7DMbbzL7chXfIk2RmSu8YblnOJ+mqckEau8yousVZ9v X-Received: by 2002:a63:1b1f:: with SMTP id b31mr13890889pgb.66.1543857423903; Mon, 03 Dec 2018 09:17:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543857423; cv=none; d=google.com; s=arc-20160816; b=rpeStG4FjETJauAuBNM36g04YvrIa1aBSCH0zLPCmfNm9EeIeAKXIi6bkgMAV9OKhb zZ1GsQKZsPnD+tuq4O9qSrg64tf/qylbLTyNLsP7Agg3l1qY5+Ml5xa4qGAkWpZtXNYI zdocP2jQZKJ0qpLK6hZ1vIlzhDN89EwboEKbfpA2pW4wiH2v3OSMbsdZU7oH8CB89AHU l1WOB0YTAvCi5eYWPNM4hVT4I27uR6VxaNQ6WI4pw9hTjqlFvGmSv33pptAQrSpNJhj0 DFs1mJsl1g6/RieHaU4Nh7lCoL1tAOioFutzyapfmraS1r4wY5iTm2xT/PZVc1ZRBYQe gDew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kB5h7/Rv1D1xOyHHlP5vWdrL7/AqkFtz/4BXIM0rK9U=; b=l9oNZF2nvMUeLNO91V1fVQ0nhU9JcTKYZJrmwwu8WKSHReD2G3uWviku6BGwH2TQet kRj0j+T/T3qCEZ3aFHzH7NjJokUaRDNfSVaC/20/knuwYDl94xpHBlZclu8gOpNZc1Jr ImlrDVou1g4w8wYwz1+SVXqp2gnXoM390Ul5W9mPZ1tm55hmOWb6lsUX5zFCYzg1hPIc YhywFhg9QGpYFVHyqDWwdag2gsnWYdKaQs/Yl/7Vetjygm+wnNXLsvpVEHKgBUUGkmSP l7Nify1C3ifWnwAqIVWqfyphP8TZUinHSO194NBIk4aTm+Jnby6zntqaBimdoveePMj/ aDeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=V9y1fEFC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z21si12219019pgv.363.2018.12.03.09.17.03; Mon, 03 Dec 2018 09:17:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=V9y1fEFC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727061AbeLCRRD (ORCPT + 6 others); Mon, 3 Dec 2018 12:17:03 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:39555 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726955AbeLCRRC (ORCPT ); Mon, 3 Dec 2018 12:17:02 -0500 Received: by mail-wm1-f65.google.com with SMTP id f81so4095832wmd.4 for ; Mon, 03 Dec 2018 09:16:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kB5h7/Rv1D1xOyHHlP5vWdrL7/AqkFtz/4BXIM0rK9U=; b=V9y1fEFCuD2h5uN7uD+DaVzIvzU86Lx4yzK6uxuJuZvEHPQcbmWNar7+BPBFt0RiPs uRKiBU5QQRJban/13TYK4baJkz4fVotz/nrqAvbhsmi+pAnPuBFjeCsYWCY8geeJ+ToC i4TyGm711cHH8ce5XBfJf+wRdW0oCYC9xcfOJAEt0RyO40tBskPSAefFQ3cBg0NT4pgB rXwt5U7kG/81STgqfrGTu+0khzDNlgDw/xlEulmgocf505qrCa04Z9l+MCPkFluTQhR4 8NSmDGwm9W0gONByiN9txLhjn21d5IWDEMBbQQAlstFiLc/dr0DwMSirS6fKhYR3LqR4 jnVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kB5h7/Rv1D1xOyHHlP5vWdrL7/AqkFtz/4BXIM0rK9U=; b=eJkumgZ+bshofFeqxSl/6PViwa8PNX4XvZf3V8geV2p2iM3tjTSezOWDDk6FW6CesO PP3MV3QwE76EEkEAyZAxwS7w5LJ8VkAjetD2sMB7rR6kY9SBhpUasftXpv+wkEZCbXKv 3iCmkJHFMYDnQXz6GG29Xs+2FC11S5BEuI0+O8brqCRUap2g/LBFxFvU6hvte4nsAL6V EYjSe4lcRAEZ/oT/DvDo++sm6EZ4tNs/Lycs5n7RJDJpIb0uyHwRk5uMQQe/dzsrBpph 43LF/JYfo/q+kYop8w0o6EBRKcgOM6al5mP+aVAe3otYx27Ewn58+fOcEzbyskI16qlu sy3w== X-Gm-Message-State: AA+aEWYfs+KKm/ld8hrJKZE0jTLZHAr9bJRSosbfDJLlJCPr/LLaavmy AQa7qSsicmkha8bKmLHDqIYCBg== X-Received: by 2002:a1c:588a:: with SMTP id m132-v6mr9040728wmb.85.1543857418700; Mon, 03 Dec 2018 09:16:58 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id h203sm22494889wma.19.2018.12.03.09.16.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 09:16:58 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] dt-bindings: clk: meson: add main controller clock input Date: Mon, 3 Dec 2018 18:16:39 +0100 Message-Id: <20181203171640.12110-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181203171640.12110-1-jbrunet@baylibre.com> References: <20181203171640.12110-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock input of the main clock controller Signed-off-by: Jerome Brunet --- .../devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) -- 2.19.1 Reviewed-by: Stephen Boyd diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; };