@@ -454,6 +454,7 @@ CAPSULE_HEADER_INIT_VERSION = 0x1
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ASL Optional |.aml
}
[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -365,6 +365,7 @@ READ_LOCK_STATUS = TRUE
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ASL Optional |.aml
}
[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -367,6 +367,7 @@ READ_LOCK_STATUS = TRUE
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ASL Optional |.aml
}
[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -28,6 +28,7 @@
[Sources]
AcpiPlatform.c
+ SsdtB1.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -39,12 +40,18 @@
[LibraryClasses]
AmdStyxAcpiLib
DebugLib
+ DxeServicesLib
+ MemoryAllocationLib
PcdLib
UefiBootServicesTableLib
UefiDriverEntryPoint
[Pcd]
gAmdStyxTokenSpaceGuid.PcdEnableSmmus
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
[Protocols]
gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED
@@ -130,41 +130,12 @@ OverrideMacAddr (
}
}
-VOID
-OverrideStatus (
- IN UINT8 *DSD_Data,
- IN BOOLEAN Enable
- )
-{
- if (Enable) {
- // AML encoding: ReturnOp + BytePrefix
- if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) {
- DSD_Data[3] = 0x0F;
- }
- } else {
- // AML encoding: ReturnOp
- if (DSD_Data[1] == 0xA4) {
- // AML encoding: BytePrefix?
- if (DSD_Data[2] == 0x0A) {
- DSD_Data[3] = 0x00;
- } else {
- DSD_Data[2] = 0x00;
- }
- }
- }
-}
-
EFI_ACPI_DESCRIPTION_HEADER *
DsdtHeader (
VOID
)
{
AML_OFFSET_TABLE_ENTRY *Table;
- BOOLEAN EnableOnB1;
- UINT32 CpuId = PcdGet32 (PcdSocCpuId);
-
- // Enable features on Styx-B1 or later
- EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F);
Table = &DSDT_SEATTLE__OffsetTable[0];
while (Table->Pathname) {
@@ -174,16 +145,6 @@ DsdtHeader (
else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) {
OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB));
}
- else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
- OverrideStatus ((UINT8 *)&AmlCode[Table->Offset],
- EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0);
- }
- else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) {
- OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
- }
- else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) {
- OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
- }
++Table;
}
@@ -24,13 +24,57 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Acpi61.h>
+
+#include <SocVersion.h>
+
#define MAX_ACPI_TABLES 16
EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES];
+STATIC EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol;
+
+STATIC
+VOID
+InstallSystemDescriptionTables (
+ VOID
+ )
+{
+ EFI_ACPI_DESCRIPTION_HEADER *Table;
+ EFI_STATUS Status;
+ UINT32 CpuId;
+ UINTN Index;
+ UINTN TableSize;
+ UINTN TableHandle;
+
+ Status = EFI_SUCCESS;
+ for (Index = 0; !EFI_ERROR (Status); Index++) {
+ Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index,
+ (VOID **) &Table, &TableSize);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ switch (Table->OemTableId) {
+ case SIGNATURE_64 ('S', 't', 'y', 'x', 'B', '1', ' ', ' '):
+ CpuId = PcdGet32 (PcdSocCpuId);
+ if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
+ continue;
+ }
+ break;
+ }
+
+ Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Table,
+ TableSize, &TableHandle);
+ ASSERT_EFI_ERROR (Status);
+ FreePool (Table);
+ }
+}
/**
Entrypoint of Acpi Platform driver.
@@ -51,7 +95,6 @@ AcpiPlatformEntryPoint (
)
{
EFI_STATUS Status;
- EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
UINTN TableHandle;
UINTN TableIndex;
@@ -77,7 +120,8 @@ AcpiPlatformEntryPoint (
//
// Find the AcpiTable protocol
//
- Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL,
+ (VOID**)&mAcpiTableProtocol);
if (EFI_ERROR (Status)) {
DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status));
ASSERT_EFI_ERROR(Status);
@@ -96,12 +140,12 @@ AcpiPlatformEntryPoint (
AcpiTableList[TableIndex]->Revision,
AcpiTableList[TableIndex]->Length));
- Status = AcpiTable->InstallAcpiTable (
- AcpiTable,
- AcpiTableList[TableIndex],
- (AcpiTableList[TableIndex])->Length,
- &TableHandle
- );
+ Status = mAcpiTableProtocol->InstallAcpiTable (
+ mAcpiTableProtocol,
+ AcpiTableList[TableIndex],
+ (AcpiTableList[TableIndex])->Length,
+ &TableHandle
+ );
if (EFI_ERROR (Status)) {
DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status));
ASSERT_EFI_ERROR(Status);
@@ -110,6 +154,8 @@ AcpiPlatformEntryPoint (
ASSERT( TableIndex < MAX_ACPI_TABLES );
}
+ InstallSystemDescriptionTables ();
+
return EFI_SUCCESS;
}
@@ -105,35 +105,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
})
}
- Device (AHC1)
- {
- Name (_HID, "AMDI0600") // _HID: Hardware ID
- Name (_UID, 0x01) // _UID: Unique ID
- Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
- Name (_CLS, Package (0x03) // _CLS: Class Code
- {
- 0x01,
- 0x06,
- 0x01
- })
- Method (_STA)
- {
- Return (0x0F)
- }
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0xE0D00000, // Address Base (MMIO)
- 0x00010000, // Address Length
- )
- Memory32Fixed (ReadWrite,
- 0xE000007C, // Address Base (SGPIO)
- 0x00000001, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
- })
- }
-
#if DO_XGBE
Device (ETH0)
{
@@ -344,44 +315,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
})
}
- Device (GIO2)
- {
- Name (_HID, "AMDI0400") // _HID: Hardware ID
- Name (_CID, "ARMH0061") // _CID: Compatible ID
- Name (_UID, 0x02) // _UID: Unique ID
- Method (_STA)
- {
- Return (0x0F)
- }
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0xE0020000, // Address Base
- 0x00001000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
- })
- }
-
- Device (GIO3)
- {
- Name (_HID, "AMDI0400") // _HID: Hardware ID
- Name (_CID, "ARMH0061") // _CID: Compatible ID
- Name (_UID, 0x03) // _UID: Unique ID
- Method (_STA)
- {
- Return (0x0F)
- }
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0xE0030000, // Address Base
- 0x00001000, // Address Length
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
- })
- }
-
Device (I2C0)
{
Name (_HID, "AMDI0510") // _HID: Hardware ID
new file mode 100644
@@ -0,0 +1,86 @@
+/** @file
+
+ SSDT for peripherals that are only enabled on B1 silicon
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock ("SsdtB1.aml", "SSDT", 2, "AMDINC", "StyxB1 ", 3)
+{
+ Scope (_SB)
+ {
+ Device (AHC1)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Method (_STA)
+ {
+ If (LEqual (FixedPcdGet8 (PcdSata1PortCount), 0)) {
+ Return (0x0)
+ }
+ Return (0xF)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0D00000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE000007C, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
+ })
+ }
+
+ Device (GIO2)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x02) // _UID: Unique ID
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
+ })
+ }
+
+ Device (GIO3)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
+ })
+ }
+ }
+}
Instead of poking DSDT _STA method bytecode to make it return something else depending on whether we are running on B1 silicon, move the B1 only peripherals to a separate SSDT and only install it when running on compatible hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 + Platform/LeMaker/CelloBoard/CelloBoard.fdf | 1 + Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 1 + Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 7 ++ Silicon/AMD/Styx/AcpiTables/Dsdt.c | 39 --------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 62 ++++++++++++-- Silicon/AMD/Styx/AcpiTables/Dsdt.asl | 67 --------------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl | 86 ++++++++++++++++++++ 8 files changed, 150 insertions(+), 114 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel