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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z61si20889200plb.49.2018.12.05.10.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Oi4aXoHY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 404522119926A; Wed, 5 Dec 2018 10:50:30 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AE02421197B2F for ; Wed, 5 Dec 2018 10:50:28 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id 96so20825616wrb.2 for ; Wed, 05 Dec 2018 10:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OetyPm3iZnHAbXn6SSPHfSYSw5LK5X81QrpMxEJIJp4=; b=Oi4aXoHYgXczd0LNIIZdh+7Ft1mTu8cXtoO7tyPqQndOySSSL3AoBrSQASwaOfHXR1 qu5xE/+sTYrjm8rXadyeRLRVFJwtduDhjUMo9rgQk4xQYQjWmX8BOUp09exTw7fVBFAB FP1jOMjpR5EkIffCft4GzpUgK36Ky6UtjFvCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OetyPm3iZnHAbXn6SSPHfSYSw5LK5X81QrpMxEJIJp4=; b=PKvGCydHHokYpD90bgV7x1RDsmq9MwhgzhLWL188rpkyQlMqTLMX8sGtBWLc1QY4XG gr7CAVmwLX3zBQJPLqPv00Q8PEi4ZjHEy+eMmae62FA0rsNdu4RBlJutJgRyKKxG2lBX zXEgUNmXv5zEcglD6qBz/h6qo8dBFBGoya2yZk6w4W4XOgJD/FT+LC17LRV0WWsbE61p Zubs4iTNC3583mUEcNZxhyawaewXfr/MeqPP+y/tKxZYIRGKESgXBnznPLyapCT3F7xB Sqi1eqVR0m7MwSIwa5xa7FToufACsalNhyYTAqll2Q204IZ8EatRKWtHQiQFTIOByckP ASuA== X-Gm-Message-State: AA+aEWbaretkZWzfmdjlQ8XHE4y52HY3S5CvhHDpFMGtMn48YMT5VbqD 9vCQHLCSDTL1ATWEecpxQl9kM6iqmZHS5w== X-Received: by 2002:adf:81b6:: with SMTP id 51mr24536311wra.240.1544035826449; Wed, 05 Dec 2018 10:50:26 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:816d:4a95:a2ca:814d]) by smtp.gmail.com with ESMTPSA id c8sm14825186wrx.42.2018.12.05.10.50.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Dec 2018 10:50:25 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 5 Dec 2018 19:50:16 +0100 Message-Id: <20181205185020.21441-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205185020.21441-1-ard.biesheuvel@linaro.org> References: <20181205185020.21441-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/6] Silicon/AMD/Styx: move B1 revision peripherals to separate SSDT table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of poking DSDT _STA method bytecode to make it return something else depending on whether we are running on B1 silicon, move the B1 only peripherals to a separate SSDT and only install it when running on compatible hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 + Platform/LeMaker/CelloBoard/CelloBoard.fdf | 1 + Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 1 + Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 7 ++ Silicon/AMD/Styx/AcpiTables/Dsdt.c | 39 --------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 62 ++++++++++++-- Silicon/AMD/Styx/AcpiTables/Dsdt.asl | 67 --------------- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl | 86 ++++++++++++++++++++ 8 files changed, 150 insertions(+), 114 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index bf4e6f3283eb..cc082031621c 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -454,6 +454,7 @@ CAPSULE_HEADER_INIT_VERSION = 0x1 DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.fdf b/Platform/LeMaker/CelloBoard/CelloBoard.fdf index 0f412ba90e54..45fc850c36cb 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.fdf +++ b/Platform/LeMaker/CelloBoard/CelloBoard.fdf @@ -365,6 +365,7 @@ READ_LOCK_STATUS = TRUE DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index 2800d5d1f536..fec3acdd767c 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -367,6 +367,7 @@ READ_LOCK_STATUS = TRUE DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 3c484c43ac41..245724aa8ea2 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -28,6 +28,7 @@ [Sources] AcpiPlatform.c + SsdtB1.asl [Packages] ArmPkg/ArmPkg.dec @@ -39,12 +40,18 @@ [LibraryClasses] AmdStyxAcpiLib DebugLib + DxeServicesLib + MemoryAllocationLib PcdLib UefiBootServicesTableLib UefiDriverEntryPoint [Pcd] gAmdStyxTokenSpaceGuid.PcdEnableSmmus + gAmdStyxTokenSpaceGuid.PcdSocCpuId + +[FixedPcd] + gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.c b/Silicon/AMD/Styx/AcpiTables/Dsdt.c index 360a446f7631..dd432ce03ad1 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.c +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.c @@ -130,41 +130,12 @@ OverrideMacAddr ( } } -VOID -OverrideStatus ( - IN UINT8 *DSD_Data, - IN BOOLEAN Enable - ) -{ - if (Enable) { - // AML encoding: ReturnOp + BytePrefix - if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) { - DSD_Data[3] = 0x0F; - } - } else { - // AML encoding: ReturnOp - if (DSD_Data[1] == 0xA4) { - // AML encoding: BytePrefix? - if (DSD_Data[2] == 0x0A) { - DSD_Data[3] = 0x00; - } else { - DSD_Data[2] = 0x00; - } - } - } -} - EFI_ACPI_DESCRIPTION_HEADER * DsdtHeader ( VOID ) { AML_OFFSET_TABLE_ENTRY *Table; - BOOLEAN EnableOnB1; - UINT32 CpuId = PcdGet32 (PcdSocCpuId); - - // Enable features on Styx-B1 or later - EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F); Table = &DSDT_SEATTLE__OffsetTable[0]; while (Table->Pathname) { @@ -174,16 +145,6 @@ DsdtHeader ( else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) { OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB)); } - else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], - EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0); - } - else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1); - } - else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) { - OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1); - } ++Table; } diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 901eac105932..0d0033b4d6c6 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -24,13 +24,57 @@ #include #include +#include +#include #include #include +#include + +#include + #define MAX_ACPI_TABLES 16 EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; +STATIC EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; + +STATIC +VOID +InstallSystemDescriptionTables ( + VOID + ) +{ + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_STATUS Status; + UINT32 CpuId; + UINTN Index; + UINTN TableSize; + UINTN TableHandle; + + Status = EFI_SUCCESS; + for (Index = 0; !EFI_ERROR (Status); Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, + (VOID **) &Table, &TableSize); + if (EFI_ERROR (Status)) { + break; + } + + switch (Table->OemTableId) { + case SIGNATURE_64 ('S', 't', 'y', 'x', 'B', '1', ' ', ' '): + CpuId = PcdGet32 (PcdSocCpuId); + if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + continue; + } + break; + } + + Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Table, + TableSize, &TableHandle); + ASSERT_EFI_ERROR (Status); + FreePool (Table); + } +} /** Entrypoint of Acpi Platform driver. @@ -51,7 +95,6 @@ AcpiPlatformEntryPoint ( ) { EFI_STATUS Status; - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; UINTN TableHandle; UINTN TableIndex; @@ -77,7 +120,8 @@ AcpiPlatformEntryPoint ( // // Find the AcpiTable protocol // - Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable); + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, + (VOID**)&mAcpiTableProtocol); if (EFI_ERROR (Status)) { DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status)); ASSERT_EFI_ERROR(Status); @@ -96,12 +140,12 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex]->Revision, AcpiTableList[TableIndex]->Length)); - Status = AcpiTable->InstallAcpiTable ( - AcpiTable, - AcpiTableList[TableIndex], - (AcpiTableList[TableIndex])->Length, - &TableHandle - ); + Status = mAcpiTableProtocol->InstallAcpiTable ( + mAcpiTableProtocol, + AcpiTableList[TableIndex], + (AcpiTableList[TableIndex])->Length, + &TableHandle + ); if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status)); ASSERT_EFI_ERROR(Status); @@ -110,6 +154,8 @@ AcpiPlatformEntryPoint ( ASSERT( TableIndex < MAX_ACPI_TABLES ); } + InstallSystemDescriptionTables (); + return EFI_SUCCESS; } diff --git a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl index 4741bb487cc7..e9991644e6a0 100644 --- a/Silicon/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Silicon/AMD/Styx/AcpiTables/Dsdt.asl @@ -105,35 +105,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) }) } - Device (AHC1) - { - Name (_HID, "AMDI0600") // _HID: Hardware ID - Name (_UID, 0x01) // _UID: Unique ID - Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_CLS, Package (0x03) // _CLS: Class Code - { - 0x01, - 0x06, - 0x01 - }) - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0D00000, // Address Base (MMIO) - 0x00010000, // Address Length - ) - Memory32Fixed (ReadWrite, - 0xE000007C, // Address Base (SGPIO) - 0x00000001, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, } - }) - } - #if DO_XGBE Device (ETH0) { @@ -344,44 +315,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) }) } - Device (GIO2) - { - Name (_HID, "AMDI0400") // _HID: Hardware ID - Name (_CID, "ARMH0061") // _CID: Compatible ID - Name (_UID, 0x02) // _UID: Unique ID - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0020000, // Address Base - 0x00001000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, } - }) - } - - Device (GIO3) - { - Name (_HID, "AMDI0400") // _HID: Hardware ID - Name (_CID, "ARMH0061") // _CID: Compatible ID - Name (_UID, 0x03) // _UID: Unique ID - Method (_STA) - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0xE0030000, // Address Base - 0x00001000, // Address Length - ) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, } - }) - } - Device (I2C0) { Name (_HID, "AMDI0510") // _HID: Hardware ID diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl new file mode 100644 index 000000000000..78aa220a0457 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/SsdtB1.asl @@ -0,0 +1,86 @@ +/** @file + + SSDT for peripherals that are only enabled on B1 silicon + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("SsdtB1.aml", "SSDT", 2, "AMDINC", "StyxB1 ", 3) +{ + Scope (_SB) + { + Device (AHC1) + { + Name (_HID, "AMDI0600") // _HID: Hardware ID + Name (_UID, 0x01) // _UID: Unique ID + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute + Name (_CLS, Package (0x03) // _CLS: Class Code + { + 0x01, + 0x06, + 0x01 + }) + Method (_STA) + { + If (LEqual (FixedPcdGet8 (PcdSata1PortCount), 0)) { + Return (0x0) + } + Return (0xF) + } + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0D00000, // Address Base (MMIO) + 0x00010000, // Address Length + ) + Memory32Fixed (ReadWrite, + 0xE000007C, // Address Base (SGPIO) + 0x00000001, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, } + }) + } + + Device (GIO2) + { + Name (_HID, "AMDI0400") // _HID: Hardware ID + Name (_CID, "ARMH0061") // _CID: Compatible ID + Name (_UID, 0x02) // _UID: Unique ID + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0020000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, } + }) + } + + Device (GIO3) + { + Name (_HID, "AMDI0400") // _HID: Hardware ID + Name (_CID, "ARMH0061") // _CID: Compatible ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xE0030000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, } + }) + } + } +}