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[198.145.21.10]) by mx.google.com with ESMTPS id n12si2469358pgb.563.2018.12.07.03.23.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Dec 2018 03:23:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ZvPSRhBO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8D03321196812; Fri, 7 Dec 2018 03:23:13 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C1A1E21962301 for ; Fri, 7 Dec 2018 03:23:11 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id c14so3488125wrr.0 for ; Fri, 07 Dec 2018 03:23:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w7VVg+yArbsU91j6JpTdvhIEl1GeUVtKoqELN4+cO8k=; b=ZvPSRhBObEooaMCLO1vjgnfYXNuVTxJab94SUIJVcfv3RQLDhO5ewghNQO+JwWOmWT 0UOWiC4uCHAB9+nZmf2jrxGUYlf3oyYxUUx4UoeRQfZl6qkZy5ElcYpWcb0ry4T8AMN3 y5aCC6m2ClKeERkjwEz2ZPqan8FCHplO3vPDk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w7VVg+yArbsU91j6JpTdvhIEl1GeUVtKoqELN4+cO8k=; b=haoZBpWo/GjPwItw0roGFl3qjkRJnrVrOrpCD9o6Rmxyo9codbeqgLqLxXCrKTpyPH 2hAQszj3ICJ6QNf0M9zagssE8OqDGcz0Qva5GC6Vh3hCmOqXO+F4hzCfB4K+TCaRgAkX QW1sdfxLijSS985XHMwmrtQjh4zV4fzjTxYAEZtBWmJt9UiSDQPqzTCDLeKUq465B/4x GXjILx8O59xBjkPzHblfdiYgvt2gPG5+RBc+3p5L2xHBtScK4RXSqGu7Xxd5HeflnOuK jd/mpMMs1qRLoQWdf2q1xQ1aZ5QwojXOdSQTZzlh+Rv57L08WiNAAtiseiDPjGmHjjMn 4CWA== X-Gm-Message-State: AA+aEWZqRaEQIX0pM1VqPWEPAuLgYhPkTzAPSVpHwNcBAmbbz3DkjEa9 BUhpTGtZZG7t9T3tnI4fKLDrQDKf/1XDwA== X-Received: by 2002:a5d:4e47:: with SMTP id r7mr1519484wrt.264.1544181790048; Fri, 07 Dec 2018 03:23:10 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:2cd0:a19e:84ff:4800]) by smtp.gmail.com with ESMTPSA id f187sm2813542wma.4.2018.12.07.03.23.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Dec 2018 03:23:09 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 7 Dec 2018 12:22:58 +0100 Message-Id: <20181207112304.19765-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181207112304.19765-1-ard.biesheuvel@linaro.org> References: <20181207112304.19765-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [RFC PATCH 1/7] MdePkg/Base: introduce MAX_ALLOC_ADDRESS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Hao Wu , Liming Gao , Michael D Kinney , Laszlo Ersek Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" On some architectures, the maximum representable address deviates from the virtual address range that is accessible by the firmware at boot time. For instance, on AArch64, UEFI mandates a 4 KB page size, which limits the address space to 48 bits, while more than that may be populated on a particular platform, for use by the OS. So introduce a new macro MAX_ALLOC_ADDRESS, which represent the maximum address the firmware should take into account when allocating memory ranges that need to be accessible by the CPU at boot time. Initially, it just defaults to MAX_ADDRESS, but later on, architectures may elect to override it to a smaller number. This means that all replacements of MAX_ADDRESS with MAX_ALLOC_ADDRESS are functional no-ops unless an architecture sets a value for the latter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- MdePkg/Include/Base.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Laszlo Ersek diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index bc877d8125a5..618f8ea85ce7 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -404,6 +404,10 @@ struct _LIST_ENTRY { #define MIN_INT32 (((INT32) -2147483647) - 1) #define MIN_INT64 (((INT64) -9223372036854775807LL) - 1) +#ifndef MAX_ALLOC_ADDRESS +#define MAX_ALLOC_ADDRESS MAX_ADDRESS +#endif + #define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004