From patchwork Mon Dec 10 16:56:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 153309 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3775989ljp; Mon, 10 Dec 2018 08:56:39 -0800 (PST) X-Google-Smtp-Source: AFSGD/VGQj/aoeevkvXscnjVXrM8Ee+M1fQqzP5OHRmDkebrPa/+ZOMndwO3RgQzMNgTppGLZ+bm X-Received: by 2002:adf:f449:: with SMTP id f9mr10797209wrp.40.1544460999614; Mon, 10 Dec 2018 08:56:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544460999; cv=none; d=google.com; s=arc-20160816; b=Gl4oUGltDSDXv6y1Osm+0xFRbxmeedAN/rkLK2kAO7yykSWwXkOJSOwGes7b59YRG/ RUvw//Xf4rbFgQECjKeSMWX4xyu3SBx/ZW09B4QckvrRc7MOaegSVUzjg51lP+WwU+zO BQlUQItmFPnlNt5vod/zHAOhkQY+8shx0HUMS/tVJZAvEkQfJI89lTlFQ622ngn4sFXf BvssjlZNArMhcVsuZyA0PtUO7BA0c1Js9slcz06aUou3gDEMFLsdIbymhLgl28togDK5 0IxyKiC5q31M8gXYmgCGsFLSd9Y6FaB/UKyLbYGGHTUlxh4gDefEjnmL7S/d/VqBLuLx 32OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=wLj/o0NUcQTORj+AHTzqhqotcmvb4BsNhXYBCSYBs9s=; b=zL89xrcKcVsm7ylmKTX+LYdufgOUGCqubYE0rhAxuU28IgNty9OSpDFibONxxxnrTf jxdLKfCDm2T0L5XwdjWEy7TT4okK7zZj0+SbyMYhWidgJCVtVfkk8Yc/Ib+wBDCSlzLH N4oUUkkdcL4fyp6AF7wfhL8ePUGOxd12a071vRuRvI79mpJcIvBD57xD8swNyjKx6L50 7mdKZKc1OEK+CBsExM6KpMGs5iJ5RqYG4CwKBFKkZTdp+kAF/IcxQoOLVEYAmcJ9DI/1 I+RQEc/J3zWoboOHdrnF3LDAvDGecrVssAWd5O2sJCAvQPZVcOhVSj1vd4BdJbbW9ZV0 neVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o8si7458746wrv.48.2018.12.10.08.56.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Dec 2018 08:56:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gWOrH-0000Mz-0D; Mon, 10 Dec 2018 16:56:39 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Laurent Vivier , Mark Cave-Ayland Subject: [RFC 3/3] target/m68k: Switch to transaction_failed hook Date: Mon, 10 Dec 2018 16:56:36 +0000 Message-Id: <20181210165636.28366-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181210165636.28366-1-peter.maydell@linaro.org> References: <20181210165636.28366-1-peter.maydell@linaro.org> MIME-Version: 1.0 Switch the m68k target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. (In previous commits we put in explicit checks for the direct physical loads made by the target/m68k code which will no longer be handled by calling the unassigned_access hook.) Signed-off-by: Peter Maydell --- target/m68k/cpu.h | 7 ++++--- target/m68k/cpu.c | 2 +- target/m68k/op_helper.c | 20 ++++++++------------ 3 files changed, 13 insertions(+), 16 deletions(-) -- 2.19.2 Reviewed-by: Laurent Vivier diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b288a3864e0..08828b0581b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -545,9 +545,10 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); -void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size); +void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #include "exec/cpu-all.h" diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b37..6d09c630b0e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -271,7 +271,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->gdb_write_register = m68k_cpu_gdb_write_register; cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault; #if defined(CONFIG_SOFTMMU) - cc->do_unassigned_access = m68k_cpu_unassigned_access; + cc->do_transaction_failed = m68k_cpu_transaction_failed; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info = m68k_cpu_disas_set_info; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8d09ed91c49..6739ab8e436 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -454,19 +454,15 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) do_interrupt_all(env, 1); } -void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, - bool is_exec, int is_asi, unsigned size) +void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; -#ifdef DEBUG_UNASSIGNED - qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", - addr, is_write, is_exec); -#endif - if (env == NULL) { - /* when called from gdb, env is NULL */ - return; - } + + cpu_restore_state(cs, retaddr, true); if (m68k_feature(env, M68K_FEATURE_M68040)) { env->mmu.mmusr = 0; @@ -476,7 +472,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, if (env->sr & SR_S) { /* SUPERVISOR */ env->mmu.ssw |= M68K_TM_040_SUPER; } - if (is_exec) { /* instruction or data */ + if (access_type == MMU_INST_FETCH) { /* instruction or data */ env->mmu.ssw |= M68K_TM_040_CODE; } else { env->mmu.ssw |= M68K_TM_040_DATA; @@ -494,7 +490,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, break; } - if (!is_write) { + if (access_type != MMU_DATA_STORE) { env->mmu.ssw |= M68K_RW_040; }