| Message ID | 20181218063911.2112-3-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg, target/ppc vector improvements | expand |
On Mon, Dec 17, 2018 at 10:38:39PM -0800, Richard Henderson wrote: > Since we're now handling a == b generically, we no longer need > to do it by hand within target/arm/. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/arm/translate-a64.c | 6 +----- > target/arm/translate-sve.c | 6 +----- > target/arm/translate.c | 12 +++--------- > 3 files changed, 5 insertions(+), 19 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index e1da1e4d6f..2d6f8c1b4f 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -10152,11 +10152,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) > gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); > return; > case 2: /* ORR */ > - if (rn == rm) { /* MOV */ > - gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0); > - } else { > - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); > - } > + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); > return; > case 3: /* ORN */ > gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index b15b615ceb..3a2eb51566 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a) > > static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) > { > - if (a->rn == a->rm) { /* MOV */ > - return do_mov_z(s, a->rd, a->rn); > - } else { > - return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); > - } > + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); > } > > static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 7c4675ffd8..33b1860148 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) > tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, > vec_size, vec_size); > break; > - case 2: > - if (rn == rm) { > - /* VMOV */ > - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size); > - } else { > - /* VORR */ > - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, > - vec_size, vec_size); > - } > + case 2: /* VORR */ > + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, > + vec_size, vec_size); > break; > case 3: /* VORN */ > tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..2d6f8c1b4f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10152,11 +10152,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); return; case 2: /* ORR */ - if (rn == rm) { /* MOV */ - gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); - } + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); return; case 3: /* ORN */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b15b615ceb..3a2eb51566 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a) static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) { - if (a->rn == a->rm) { /* MOV */ - return do_mov_z(s, a->rd, a->rn); - } else { - return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); - } + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); } static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c4675ffd8..33b1860148 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); break; - case 2: - if (rn == rm) { - /* VMOV */ - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size); - } else { - /* VORR */ - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } + case 2: /* VORR */ + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); break; case 3: /* VORN */ tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
Since we're now handling a == b generically, we no longer need to do it by hand within target/arm/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 6 +----- target/arm/translate-sve.c | 6 +----- target/arm/translate.c | 12 +++--------- 3 files changed, 5 insertions(+), 19 deletions(-) -- 2.17.2