diff mbox series

[32/34] target/ppc: Split out VSCR_SAT to a vector field

Message ID 20181218063911.2112-33-richard.henderson@linaro.org
State New
Headers show
Series tcg, target/ppc vector improvements | expand

Commit Message

Richard Henderson Dec. 18, 2018, 6:39 a.m. UTC
Change the representation of VSCR_SAT such that it is easy
to set from vector code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/ppc/cpu.h        |  4 +++-
 target/ppc/int_helper.c | 11 ++++++++---
 2 files changed, 11 insertions(+), 4 deletions(-)

-- 
2.17.2

Comments

David Gibson Dec. 19, 2018, 6:41 a.m. UTC | #1
On Mon, Dec 17, 2018 at 10:39:09PM -0800, Richard Henderson wrote:
> Change the representation of VSCR_SAT such that it is easy

> to set from vector code.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Acked-by: David Gibson <david@gibson.dropbear.id.au>


> ---

>  target/ppc/cpu.h        |  4 +++-

>  target/ppc/int_helper.c | 11 ++++++++---

>  2 files changed, 11 insertions(+), 4 deletions(-)

> 

> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h

> index a2fe6058b1..26d2e16720 100644

> --- a/target/ppc/cpu.h

> +++ b/target/ppc/cpu.h

> @@ -1063,10 +1063,12 @@ struct CPUPPCState {

>      /* Special purpose registers */

>      target_ulong spr[1024];

>      ppc_spr_t spr_cb[1024];

> -    /* Vector status and control register */

> +    /* Vector status and control register, minus VSCR_SAT.  */

>      uint32_t vscr;

>      /* VSX registers (including FP and AVR) */

>      ppc_vsr_t vsr[64] QEMU_ALIGNED(16);

> +    /* Non-zero if and only if VSCR_SAT should be set.  */

> +    ppc_vsr_t vscr_sat;

>      /* SPE registers */

>      uint64_t spe_acc;

>      uint32_t spe_fscr;

> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c

> index 38aa3e85a6..9dbcbcd87a 100644

> --- a/target/ppc/int_helper.c

> +++ b/target/ppc/int_helper.c

> @@ -471,18 +471,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh)

>  

>  void helper_mtvscr(CPUPPCState *env, uint32_t vscr)

>  {

> -    env->vscr = vscr;

> +    env->vscr = vscr & ~(1u << VSCR_SAT);

> +    /* Which bit we set is completely arbitrary, but clear the rest.  */

> +    env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);

> +    env->vscr_sat.u64[1] = 0;

>      set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);

>  }

>  

>  uint32_t helper_mfvscr(CPUPPCState *env)

>  {

> -    return env->vscr;

> +    uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;

> +    return env->vscr | (sat << VSCR_SAT);

>  }

>  

>  static inline void set_vscr_sat(CPUPPCState *env)

>  {

> -    env->vscr |= 1 << VSCR_SAT;

> +    /* The choice of non-zero value is arbitrary.  */

> +    env->vscr_sat.u32[0] = 1;

>  }

>  

>  void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a2fe6058b1..26d2e16720 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1063,10 +1063,12 @@  struct CPUPPCState {
     /* Special purpose registers */
     target_ulong spr[1024];
     ppc_spr_t spr_cb[1024];
-    /* Vector status and control register */
+    /* Vector status and control register, minus VSCR_SAT.  */
     uint32_t vscr;
     /* VSX registers (including FP and AVR) */
     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
+    /* Non-zero if and only if VSCR_SAT should be set.  */
+    ppc_vsr_t vscr_sat;
     /* SPE registers */
     uint64_t spe_acc;
     uint32_t spe_fscr;
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 38aa3e85a6..9dbcbcd87a 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -471,18 +471,23 @@  void helper_lvsr(ppc_avr_t *r, target_ulong sh)
 
 void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
 {
-    env->vscr = vscr;
+    env->vscr = vscr & ~(1u << VSCR_SAT);
+    /* Which bit we set is completely arbitrary, but clear the rest.  */
+    env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
+    env->vscr_sat.u64[1] = 0;
     set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
 }
 
 uint32_t helper_mfvscr(CPUPPCState *env)
 {
-    return env->vscr;
+    uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
+    return env->vscr | (sat << VSCR_SAT);
 }
 
 static inline void set_vscr_sat(CPUPPCState *env)
 {
-    env->vscr |= 1 << VSCR_SAT;
+    /* The choice of non-zero value is arbitrary.  */
+    env->vscr_sat.u32[0] = 1;
 }
 
 void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)