From patchwork Wed Dec 19 11:03:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154248 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4798353ljp; Wed, 19 Dec 2018 03:05:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/UyoMGRdnGMbuoxglZrSMdwUnKL+sRXLzqvoN0nz0WsJEcox0rf6lhPhTsmWCqCoEZsTc+V X-Received: by 2002:a17:906:7751:: with SMTP id o17-v6mr15938255ejn.15.1545217513467; Wed, 19 Dec 2018 03:05:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217513; cv=none; d=google.com; s=arc-20160816; b=NhTzX/QbnUrLUmg4Xm2bDYgqEcmNQNYbDxwlYLH02MP72Okm1Ej9uSoVwJcpdkhyuS Q5hZMR/sPvgzjAIZxN/1uBlBdGk5Tf4Q9oiBwqpotoHXNdP9VpiZlkAdwZUIAOwEtOXw CJOEH8A37e2Z9H5JYm2DFrA4lN1Sl1XYdXCDns94YsnFY2Jq3+Ohv7RDYOZrY4rrEzgQ XZS7f/WjvwvMENNd9TdGhKdWvF2+YBuPPLfByCVRHLbIR5g94M9G3s1AR56ghuEyEyC9 9EBCKO/8XGR9ZwxrFzRp2pvMHCciExePEFjdYJle4TZT47s7T6dpa6s3MpXCmHF/rUOK LSwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter; bh=C1OcI6wvQ/22w1Xo8N9kRnTEvHngM2rsvdRXo+zkKFI=; b=gHioSlO6dNUKqX+XvCUjjjV0olT5UVY7ALUhRfP5w7nORmdPK89D7rDpyIyEHl9I5H gb53/xFSq2H74Uu367AW87/RYuemtII4vW6bxu2wsa1Y7vQfSmDN4ymrOaO6qQzaCiAU w2rzVJv0f7ttkgXg1FEmomVyDtOk8Mkqg1ad32NBOlBpZ7UO9gQmdoahP62CWYaTm3rw fa1/wJ4Z4WioIM+UAMNrdbdL0EmIhSwMXSJNBbzj30nIW72OT2d1f0/bW0K08bbS34jE w6xl15j7mNk/THS4i5knq7XEoGLLdCKait9K7SbuxsHmyN8vUFb5pQveElIEy+2dJwlq xJbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ewg2z+ca; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 2-v6si682126eju.12.2018.12.19.03.05.13; Wed, 19 Dec 2018 03:05:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ewg2z+ca; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 13069C2206E; Wed, 19 Dec 2018 11:04:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 11364C21FAC; Wed, 19 Dec 2018 11:03:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AAD96C21EB4; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 9C70FC21EB4 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMR001192; Wed, 19 Dec 2018 20:03:32 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMR001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217412; bh=kI8BrC+eRpj5euVzqD134Vlct7zMawBiVlttfrkFOFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ewg2z+camoEbXDooly5BDZAyLKHbD1r+7mSrdTNVKcsdt5HvxVEUaOuWdh+kjf6CC NJ8gHsDtPJdhXLdg63cQ6NZqkAWC/VlW+JwqjC9TS0bOkhmRddSo/RtXkl9oD7FXz5 jabMhpR1znJUEGEiRFRvUwg794m3ZORsGMVWdcXhw6l47xMhhXQsm+uztEeLTnqgQb 4HmMnS12jWM2r9dbNuBN3t4BmsX8w4hXia8XeABQ0NPB+yzMQHhr5Gq3CF0AKIyOKM lMdTKJfIdxDTdYNVR+NqEl3SKkz47hUMxR2P1Cj+36HKvQcL57EfQG3AFndXctiXis OeE5+nGVTscHw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:20 +0900 Message-Id: <1545217401-27018-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 8/9] clk: uniphier: add NAND 200MHz clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 9e087b6..487b43e 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -6,13 +6,12 @@ #include "clk-uniphier.h" -/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { @@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */