From patchwork Wed Dec 19 11:03:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 154253 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4801609ljp; Wed, 19 Dec 2018 03:08:09 -0800 (PST) X-Google-Smtp-Source: AFSGD/U5NWiymRjncNFPYzjdK8IUZ4Iy3uZYBIkZoNxKzIazaYV7DOHgDET/xlIF4BtDDrCt6IKl X-Received: by 2002:aa7:df07:: with SMTP id c7mr19561915edy.85.1545217689419; Wed, 19 Dec 2018 03:08:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545217689; cv=none; d=google.com; s=arc-20160816; b=Ej+XRW4gooENZz3ozrxgDnnQy2Nq74ypbulQaWD3R7mHMK179k7yP3vVEl70ixzEEV Of00EN4paxPQjD9g12dI/K8/fGXGkn9DjEjxMx9fbAbZXPd/TUhZ4yDB0U5xFuRsg50+ S76K2GqjTbNl1PajMiSxJzaUfmOvgHliSPTgT4oJeWguNQWlx8kwlF/dXhVY7kF0EYBK cOJSYiMFI/e3XLMiecnk6vWS+zD7AFYnZzMU8tMbJ7bh+kzl5MnmNDD2W6kjn5xuouys 8edzqGwCeobxKrHqRLByqKzHD6C8d8/zn+fpez6X4vyWP8WQq9qpvUrdrQbSghmimN1d f23A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter; bh=f9gjF6pneqctTeYX+t8D76E/CHa0Pkd+/bagTXjTA6w=; b=csWAKEzgCdWmK3zk52U0gNjFC85hW9XBkopCmSVc6gYn4UoZ1TBYSTpam/07bNT/fP 4bIKbg3/iUVAg42zAdlrJnnnTUIjEYI1Q6ExTNJDHGKtUEIGw63Ew+Ii5TO+Ry2WxYmB vbHC2xCj96nnSm/0d0/hluIJt3M+aOCxHiBg2jLRRJcy/qP386IIx/8HsY03uzd+74eX yTt9oWXt77CWzMQeF35Z5plLkDmFIVVcHe1TBplvdI5U7gQrJ4vDGGDJYPjLhhji0IUk lIPj6W/Q1Dl6AkReVDMyQJBaIdQPHirETYCyITK+xGqAz7ZlvPo6rJNLOfF3nruylwwJ Jm3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=q8nXZE37; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z13-v6si2322955ejw.113.2018.12.19.03.08.09; Wed, 19 Dec 2018 03:08:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=q8nXZE37; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 0EAA6C21F85; Wed, 19 Dec 2018 11:05:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9C960C22075; Wed, 19 Dec 2018 11:03:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7E31C21EB4; Wed, 19 Dec 2018 11:03:47 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id A495DC21F49 for ; Wed, 19 Dec 2018 11:03:46 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id wBJB3SMO001192; Wed, 19 Dec 2018 20:03:31 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com wBJB3SMO001192 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1545217411; bh=wZfAZHAzS2eUfIfn3ZsjWgEB8Hk8ivMnltTOXclEsAk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q8nXZE37wv3ALiy4kVin11Ji/v08bou/wlIQEmQ38JGtlql0dAbw7+i9B1fdnL3a4 C2TCd533yvu7YFAzCC5W1847jjawmwGjp2478VHTicuQ2m/XuIZr91HJC7kvqRVjFC Bnbtg/FAI8bSSUxuBW64I0oA21VhQr+mOseXtzz/6pXvGXX9pbPkHFRs3PPDvRkZ5x 19uHWxvqwyOcYzfCCTQm52oSfVA/krk8kv2gO/87VFOk+4tVwDwr2+57e0Pk/cL5Sl hAd8st2FFxliPx8pSIfbx2bO+eXRGzgotnCBzoOU4PXzdjK1S9chx0lWFU7Vmf62w2 +EdARAGIBv4Tg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 19 Dec 2018 20:03:17 +0900 Message-Id: <1545217401-27018-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> References: <1545217401-27018-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 5/9] mtd: rawnand: denali_dt: add more clocks based on IP datasheet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5 Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run This commit supports these named clocks to represent the real hardware. For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali_dt.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 65a7797..f9eadb4 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk; + struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,15 +87,47 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_name(dev, "nand", &clk); + if (ret) + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; + ret = clk_get_by_name(dev, "nand_x", &clk_x); + if (ret) + clk_x.dev = NULL; + + ret = clk_get_by_name(dev, "ecc", &clk_ecc); + if (ret) + clk_ecc.dev = NULL; + ret = clk_enable(&clk); if (ret) return ret; - denali->clk_x_rate = clk_get_rate(&clk); + if (clk_x.dev) { + ret = clk_enable(&clk_x); + if (ret) + return ret; + } + + if (clk_ecc.dev) { + ret = clk_enable(&clk_ecc); + if (ret) + return ret; + } + + if (clk_x.dev) { + denali->clk_x_rate = clk_get_rate(&clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_x_rate = 200000000; + } return denali_init(denali); }