[edk2] ArmPkg/ArmGicV3Dxe: use correct value for ARM_GICD_IROUTER

Message ID 20181221150848.4783-1-ard.biesheuvel@linaro.org
State New
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Series
  • [edk2] ArmPkg/ArmGicV3Dxe: use correct value for ARM_GICD_IROUTER
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Commit Message

Ard Biesheuvel Dec. 21, 2018, 3:08 p.m.
Use the correct value for ARM_GICD_IROUTER as per the GIC spec,
and fix the code that relies on the value being skewed by 32 x 8
bytes.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 ArmPkg/Include/Library/ArmGicLib.h        | 2 +-
 ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.19.2

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Comments

Leif Lindholm Jan. 14, 2019, 11:24 a.m. | #1
On Fri, Dec 21, 2018 at 04:08:48PM +0100, Ard Biesheuvel wrote:
> Use the correct value for ARM_GICD_IROUTER as per the GIC spec,

> and fix the code that relies on the value being skewed by 32 x 8

> bytes.

> 

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---

>  ArmPkg/Include/Library/ArmGicLib.h        | 2 +-

>  ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +-

>  2 files changed, 2 insertions(+), 2 deletions(-)

>

> diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h

> index 5775905ca91b..b52b77628ae1 100644

> --- a/ArmPkg/Include/Library/ArmGicLib.h

> +++ b/ArmPkg/Include/Library/ArmGicLib.h

> @@ -43,7 +43,7 @@

>  #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register

>  

>  // GICv3 specific registers

> -#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers

> +#define ARM_GICD_IROUTER        0x6000 // Interrupt Routing Registers


Actually, whilst I agree the above would be more consistent, both
revisions C and D of ARM IHI 0069 list the address offset of
ARM_GICD_IROUTER as 0x6100 (and the preceding register space as
"Reserved").

/
    Leif

>  

>  // GICD_CTLR bits

>  #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)

> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

> index 1558db31713a..7d891873ba82 100644

> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

> @@ -466,7 +466,7 @@ GicV3DxeInitialize (

>      }

>  

>      // Route the SPIs to the primary CPU. SPIs start at the INTID 32

> -    for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {

> +    for (Index = 32; Index < mGicNumInterrupts; Index++) {

>        MmioWrite32 (

>          mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),

>          CpuTarget

> -- 

> 2.19.2

> 

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Ard Biesheuvel Jan. 14, 2019, 3:22 p.m. | #2
On Mon, 14 Jan 2019 at 12:24, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>

> On Fri, Dec 21, 2018 at 04:08:48PM +0100, Ard Biesheuvel wrote:

> > Use the correct value for ARM_GICD_IROUTER as per the GIC spec,

> > and fix the code that relies on the value being skewed by 32 x 8

> > bytes.

> >

> > Contributed-under: TianoCore Contribution Agreement 1.1

> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> > ---

> >  ArmPkg/Include/Library/ArmGicLib.h        | 2 +-

> >  ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +-

> >  2 files changed, 2 insertions(+), 2 deletions(-)

> >

> > diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h

> > index 5775905ca91b..b52b77628ae1 100644

> > --- a/ArmPkg/Include/Library/ArmGicLib.h

> > +++ b/ArmPkg/Include/Library/ArmGicLib.h

> > @@ -43,7 +43,7 @@

> >  #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register

> >

> >  // GICv3 specific registers

> > -#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers

> > +#define ARM_GICD_IROUTER        0x6000 // Interrupt Routing Registers

>

> Actually, whilst I agree the above would be more consistent, both

> revisions C and D of ARM IHI 0069 list the address offset of

> ARM_GICD_IROUTER as 0x6100 (and the preceding register space as

> "Reserved").

>


OK, in that case, please disregard this patch.
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Patch

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 5775905ca91b..b52b77628ae1 100644
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -43,7 +43,7 @@ 
 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
 
 // GICv3 specific registers
-#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
+#define ARM_GICD_IROUTER        0x6000 // Interrupt Routing Registers
 
 // GICD_CTLR bits
 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 1558db31713a..7d891873ba82 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -466,7 +466,7 @@  GicV3DxeInitialize (
     }
 
     // Route the SPIs to the primary CPU. SPIs start at the INTID 32
-    for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
+    for (Index = 32; Index < mGicNumInterrupts; Index++) {
       MmioWrite32 (
         mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
         CpuTarget