[13/17] target/arm: Set PSTATE.TCO on exception entry

Message ID 20190114011122.5995-14-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Implement ARMv8.5-MemTag
Related show

Commit Message

Richard Henderson Jan. 14, 2019, 1:11 a.m.
R0085 specifies that exception handlers begin with tag checks overridden.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.2

Comments

Peter Maydell Feb. 7, 2019, 5:44 p.m. | #1
On Mon, 14 Jan 2019 at 01:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> R0085 specifies that exception handlers begin with tag checks overridden.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/helper.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index df43deb0f8..1e9ccf0b2e 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)

>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",

>                    env->elr_el[new_el]);

>

> -    pstate_write(env, PSTATE_DAIF | new_mode);

> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);

>      env->aarch64 = 1;

>      aarch64_restore_sp(env, new_el);


PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,
right?

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM
Richard Henderson Feb. 8, 2019, 5:16 p.m. | #2
On 2/7/19 9:44 AM, Peter Maydell wrote:
> On Mon, 14 Jan 2019 at 01:12, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> R0085 specifies that exception handlers begin with tag checks overridden.

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>  target/arm/helper.c | 2 +-

>>  1 file changed, 1 insertion(+), 1 deletion(-)

>>

>> diff --git a/target/arm/helper.c b/target/arm/helper.c

>> index df43deb0f8..1e9ccf0b2e 100644

>> --- a/target/arm/helper.c

>> +++ b/target/arm/helper.c

>> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)

>>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",

>>                    env->elr_el[new_el]);

>>

>> -    pstate_write(env, PSTATE_DAIF | new_mode);

>> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);

>>      env->aarch64 = 1;

>>      aarch64_restore_sp(env, new_el);

> 

> PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,

> right?


TCO does not exist before MTE.  I shouldn't set it without MTE, I think, as
it's visible to the guest.

r~

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index df43deb0f8..1e9ccf0b2e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8830,7 +8830,7 @@  static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
                   env->elr_el[new_el]);
 
-    pstate_write(env, PSTATE_DAIF | new_mode);
+    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);
     env->aarch64 = 1;
     aarch64_restore_sp(env, new_el);