diff mbox series

[4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions

Message ID 20190129132335.30695-5-srinivas.kandagatla@linaro.org
State New
Headers show
Series [1/6] arm64: dts: msm8996: Add graphics smmu node | expand

Commit Message

Srinivas Kandagatla Jan. 29, 2019, 1:23 p.m. UTC 
From: Jordan Crouse <jcrouse@codeaurora.org>


Add an initial node for the Adreno GPU and it's companion
SMMU. The GPU node is mostly complete except for a bare
bones power table that will be filled out more completely
later.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

[Remove mmagic clocks from GPU/smmu nodes]
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

-- 
2.20.1

Comments

Srinivas Kandagatla Jan. 29, 2019, 5:46 p.m. UTC | #1 
Thanks Jordan,

On 29/01/2019 16:43, Jordan Crouse wrote:
> Ugh, I just found them sitting unsent in a dusty git branch. I can either send

> them as incremental patches on top of yours to be squashed later or I can

> refactor this patch and send it out again, whatever is easiest for you.


If you can refactor this patch and send it out, that would be great!

thanks,
srini
Srinivas Kandagatla Jan. 30, 2019, 10:54 a.m. UTC | #2 
Thanks Vivek,

On 30/01/2019 05:32, Vivek Gautam wrote:
> Hi,

> 

> On Wed, Jan 30, 2019 at 5:29 AM Jordan Crouse<jcrouse@codeaurora.org>  wrote:

>> Add an initial node for the Adreno GPU and it's companion

>> SMMU.

> The SMMU node is in another patch, so may be change the title of this

> patch and update the commit text too?

> 


I will update this and send v2 of the series!

--srini
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0d0b9482aa4d..b5f23594905c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@ 
 			qcom,client-id = <1>;
 			qcom,vmid = <15>;
 		};
+
+		zap_shader_region: gpu@8f200000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x90b00000 0x0 0xa00000>;
+			no-map;
+		};
 	};
 
 	cpus {
@@ -1338,6 +1344,52 @@ 
 			};
 		};
 
+		gpu@b00000 {
+			compatible = "qcom,adreno-530.2", "qcom,adreno";
+			#stream-id-cells = <16>;
+
+			reg = <0xb00000 0x3f000>;
+			reg-names = "kgsl_3d0_reg_memory";
+
+			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+
+			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+				<&mmcc GPU_AHB_CLK>,
+				<&mmcc GPU_GX_RBBMTIMER_CLK>,
+				<&gcc GCC_BIMC_GFX_CLK>,
+				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+			clock-names = "core",
+				"iface",
+				"rbbmtimer",
+				"mem",
+				"mem_iface";
+
+			power-domains = <&mmcc GPU_GDSC>;
+			iommus = <&adreno_smmu 0>;
+
+			qcom,gpu-quirk-two-pass-use-wfi;
+			qcom,gpu-quirk-fault-detect-mask;
+
+			/* This is a safe speed for bring up in all bin levels.
+			 * This isn't the fastest the chip can go, but we can
+			 * get there eventually */
+			qcom,gpu-pwrlevels {
+				compatible = "qcom,gpu-pwrlevels";
+				qcom,gpu-pwrlevel@0 {
+					qcom,gpu-freq = <510000000>;
+				};
+				qcom,gpu-pwrlevel@1 {
+					qcom,gpu-freq = <27000000>;
+				};
+			};
+
+			zap-shader {
+				memory-region = <&zap_shader_region>;
+			};
+		};
+
 		mdss: mdss@900000 {
 			compatible = "qcom,mdss";