From patchwork Fri Feb 8 08:08:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157811 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664237jaa; Fri, 8 Feb 2019 00:10:26 -0800 (PST) X-Google-Smtp-Source: AHgI3IbSMCrTuiuzdX7TuZS0ohKyDu9buItSgnDIoOqHyBibdB3aPrMWT8lD9BQHStR1ZNCXPhMa X-Received: by 2002:a65:4807:: with SMTP id h7mr2738505pgs.15.1549613426043; Fri, 08 Feb 2019 00:10:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613426; cv=none; d=google.com; s=arc-20160816; b=ae3QdhaZcUk0HGBgzEiKib406zv3BZWO8bT7F8nEC0X2GyDEKLCIhLFqIeC7efuyT8 xlrh9ZLVv7zv4oy51e3eGRmqVTHkvDEkV9fX6wdHHV/bhNFYcn25nVvTylw99jiNIMs5 k/nRlTGwEl9/DYJeSUuJHo9vAyO1sE1tjvgve3IRc7E/Dh9LY1Zr5D4+zAHpwJ7m4mYB Hx2iN0CM8l59aNdxpS30a3F8pZ4J3JniFG4OEzhrQFGQ0ke3cQNUrZCmy/nOukP9HMsH S1hO7CfOWPimfLjhm71OEMDqYSLbiOEcg7SkL37uBbVrh/J6CPNzVsO+9DodFfDdDVLE KLvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=FWcCJjEq8f/6i4xahnidBxZk+rUMKWgh+Bly4jpfp0o=; b=JXn/Tez/pWy4OwtoLSOPd2fpizuFPckwwaDPYmp0vSHH5auSQYmyoTw9fTvhcht86M sCFC0jPS4h6UWX6wGTXnqpqVQVYaXN+h/tckRUZg1lPM8WK6xKv0uk+vCDkysNkhNksW 1f7I6Hb3Oh2uy3pFykq4if42XvXoznknjB5aOSJdeeU5rGkIu4pl9fnK/49fQCe8Weko RdLHVJVSRgRUUrAOOawz+yPz2WE9BXQgJXzBdBgSyz4M1Pk/tNWUUAu2bAiBQmt2SYuw fUhDM2J5yDYZmHICnvWecGv/R8NhXl3OJin7p8EpIq4Nd93/TgDOk0hUSXUFOW44hfjk KbDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=olVwhAsp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d25si1600302pgd.88.2019.02.08.00.10.25; Fri, 08 Feb 2019 00:10:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=olVwhAsp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727383AbfBHIKY (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:24 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:61726 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727174AbfBHIKP (ORCPT ); Fri, 8 Feb 2019 03:10:15 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902E007241; Fri, 8 Feb 2019 17:09:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902E007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613346; bh=FWcCJjEq8f/6i4xahnidBxZk+rUMKWgh+Bly4jpfp0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=olVwhAspSguC9wwqWq2B51Gt4JLcqpKdPCzHgVByZ+2JUdyZPlxBB/hDLea1kytp6 FstQkB/ReKmGXLuxencnsxsS6T+Pfg2JBxsuupXK41Ev+IsO/QpzW8b0Q9oBMbR4Sg ZM91WfyHzKNzgDLuHp2pHbck9rAIfXwtbMoNa6tTyzDtFChq/hRcsCHNPfb33cuZDb glULfOnRdlUbYDSAQJ0agDI92GfLAVRUp081RrhouPZpJ4D0/SOdaEmNdzzh3cfI3r rzEb2EWRyD7XNCZPwkG/pI8EzHmUDI2pIn9YrOKNylY10xz41HaPM1+307KZgxa/qD 9En1x9qqcBnmA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 05/11] mtd: rawnand: denali: rename irq_status to irq_stat Date: Fri, 8 Feb 2019 17:08:49 +0900 Message-Id: <1549613335-30319-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I will add the third argument to denali_wait_for_irq() in the following commit. Then, some lines will exceed 80 columns. Rename 'irq_status' to 'irq_stat'. Saving two characters will avoid line-wrapping in some places, and keep the code clean. I replaced uint32_t with u32 in the touched lines. This will reduce the reports from 'scripts/checkpatch.pl --strict'. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 60 +++++++++++++++++++++---------------------- drivers/mtd/nand/raw/denali.h | 4 +-- 2 files changed, 32 insertions(+), 32 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index bd7df25..9e63cbd 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -121,10 +121,10 @@ static void denali_disable_irq(struct denali_nand_info *denali) } static void denali_clear_irq(struct denali_nand_info *denali, - int bank, uint32_t irq_status) + int bank, u32 irq_stat) { /* write one to clear bits */ - iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); + iowrite32(irq_stat, denali->reg + INTR_STATUS(bank)); } static void denali_clear_irq_all(struct denali_nand_info *denali) @@ -139,24 +139,24 @@ static irqreturn_t denali_isr(int irq, void *dev_id) { struct denali_nand_info *denali = dev_id; irqreturn_t ret = IRQ_NONE; - uint32_t irq_status; + u32 irq_stat; int i; spin_lock(&denali->irq_lock); for (i = 0; i < DENALI_NR_BANKS; i++) { - irq_status = ioread32(denali->reg + INTR_STATUS(i)); - if (irq_status) + irq_stat = ioread32(denali->reg + INTR_STATUS(i)); + if (irq_stat) ret = IRQ_HANDLED; - denali_clear_irq(denali, i, irq_status); + denali_clear_irq(denali, i, irq_stat); if (i != denali->active_bank) continue; - denali->irq_status |= irq_status; + denali->irq_stat |= irq_stat; - if (denali->irq_status & denali->irq_mask) + if (denali->irq_stat & denali->irq_mask) complete(&denali->complete); } @@ -170,7 +170,7 @@ static void denali_reset_irq(struct denali_nand_info *denali) unsigned long flags; spin_lock_irqsave(&denali->irq_lock, flags); - denali->irq_status = 0; + denali->irq_stat = 0; denali->irq_mask = 0; spin_unlock_irqrestore(&denali->irq_lock, flags); } @@ -179,16 +179,16 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) { unsigned long time_left, flags; - uint32_t irq_status; + u32 irq_stat; spin_lock_irqsave(&denali->irq_lock, flags); - irq_status = denali->irq_status; + irq_stat = denali->irq_stat; - if (irq_mask & irq_status) { + if (irq_mask & irq_stat) { /* return immediately if the IRQ has already happened. */ spin_unlock_irqrestore(&denali->irq_lock, flags); - return irq_status; + return irq_stat; } denali->irq_mask = irq_mask; @@ -203,7 +203,7 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, return 0; } - return denali->irq_status; + return denali->irq_stat; } static void denali_select_target(struct nand_chip *chip, int cs) @@ -294,7 +294,7 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, unsigned int err_byte, err_sector, err_device; uint8_t err_cor_value; unsigned int prev_sector = 0; - uint32_t irq_status; + u32 irq_stat; denali_reset_irq(denali); @@ -349,8 +349,8 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, * Once handle all ECC errors, controller will trigger an * ECC_TRANSACTION_DONE interrupt. */ - irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); - if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) + irq_stat = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); + if (!(irq_stat & INTR__ECC_TRANSACTION_DONE)) return -EIO; return max_bitflips; @@ -408,7 +408,7 @@ static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; - uint32_t irq_status, ecc_err_mask; + u32 irq_stat, ecc_err_mask; int i; if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) @@ -421,21 +421,21 @@ static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, for (i = 0; i < size / 4; i++) buf[i] = denali->host_read(denali, addr); - irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); - if (!(irq_status & INTR__PAGE_XFER_INC)) + irq_stat = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); + if (!(irq_stat & INTR__PAGE_XFER_INC)) return -EIO; - if (irq_status & INTR__ERASED_PAGE) + if (irq_stat & INTR__ERASED_PAGE) memset(buf, 0xff, size); - return irq_status & ecc_err_mask ? -EBADMSG : 0; + return irq_stat & ecc_err_mask ? -EBADMSG : 0; } static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; - uint32_t irq_status; + u32 irq_stat; int i; denali_reset_irq(denali); @@ -443,9 +443,9 @@ static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, for (i = 0; i < size / 4; i++) denali->host_write(denali, addr, buf[i]); - irq_status = denali_wait_for_irq(denali, + irq_stat = denali_wait_for_irq(denali, INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); - if (!(irq_status & INTR__PROGRAM_COMP)) + if (!(irq_stat & INTR__PROGRAM_COMP)) return -EIO; return 0; @@ -464,7 +464,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, size_t size, int page, int write) { dma_addr_t dma_addr; - uint32_t irq_mask, irq_status, ecc_err_mask; + u32 irq_mask, irq_stat, ecc_err_mask; enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; int ret = 0; @@ -501,17 +501,17 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); - irq_status = denali_wait_for_irq(denali, irq_mask); - if (!(irq_status & INTR__DMA_CMD_COMP)) + irq_stat = denali_wait_for_irq(denali, irq_mask); + if (!(irq_stat & INTR__DMA_CMD_COMP)) ret = -EIO; - else if (irq_status & ecc_err_mask) + else if (irq_stat & ecc_err_mask) ret = -EBADMSG; iowrite32(0, denali->reg + DMA_ENABLE); dma_unmap_single(denali->dev, dma_addr, size, dir); - if (irq_status & INTR__ERASED_PAGE) + if (irq_stat & INTR__ERASED_PAGE) memset(buf, 0xff, size); return ret; diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index c8c2620..46296f2 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -299,9 +299,9 @@ struct denali_nand_info { void __iomem *reg; /* Register Interface */ void __iomem *host; /* Host Data/Command Interface */ struct completion complete; - spinlock_t irq_lock; /* protect irq_mask and irq_status */ + spinlock_t irq_lock; /* protect irq_mask and irq_stat */ u32 irq_mask; /* interrupts we are waiting for */ - u32 irq_status; /* interrupts that have happened */ + u32 irq_stat; /* interrupts that have happened */ int irq; void *buf; /* for syndrome layout conversion */ int dma_avail; /* can support DMA? */