From patchwork Fri Feb 8 12:25:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157822 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1891394jaa; Fri, 8 Feb 2019 04:24:59 -0800 (PST) X-Google-Smtp-Source: AHgI3IY0KnhztkTkwVlV+lWRZlEnVSwN43DOLDIZgcFOXcVv4rrpi0Fz7IrOxpnTZs6Mrg85hwfq X-Received: by 2002:a17:902:22f:: with SMTP id 44mr22405033plc.137.1549628699395; Fri, 08 Feb 2019 04:24:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628699; cv=none; d=google.com; s=arc-20160816; b=iHf8ljV7565V2/RSy9ZLh5Vopq5JdP5zdlA5BQWvn7B4FIqbjOhDuCRSZRDme2eCCp sVz6qJBpqJJCdn8a+oOUHCh9hAOL7NZ9ne1cqfNdCYlTolmRK5gRD3f73+eWAqvC+3oh V84bEK/BTNi75mzmS/lUt0O8KlR3UkRvoXcgdjV83Ml7dpQHNlY67JbPWCtllcFB/n0P WNe4po9b2Ih67gYWyjTEcTHcU+BTTYQDDUn5slzwoBvnSq81EJ4kvxl7Hj6+g4egsMf/ eHhs+EUWdPTqIOUgzy5EiWypdmFh+4/iA+RbBOxTcaq9tuEaQKR4qNNT1aS/GTSkViAY 62sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=DLHipWaF3jlKj0cjOAMU3c4VREkUT5SIf5vOg84cLnI=; b=pAJJTL3J+/2RoVFVhuiQPJXXZh2XVmYIgaVNTPGN+RIGINy2JJwDSIov0plXuVN49M g5CK+jiQDF9z1ev0rED8aIcbWTR2/Edtwt1kko+ZALbhxdf02kLWpiJNPV+N4HJxo6Bj L1TuFhKRf8po1TDNDtPWe2NnTeycZxLnqmFULCuG+gtFKmkC+CEikcv9+vOU0KAY0S87 EXSjklRPbyvP+R2cT6wGMGIODWc0FvQ/6YbvFoKZ+bBzJ/co80klL94zcX6dVRWGkRCf ZBxCaqN9SdCiQwyO8NhLLXktfFMj/YxfBXoNcH3IiJ+vz/DePdtaNxpO54ekJ9P7BX2R A9HQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l24si2035964pgj.171.2019.02.08.04.24.59; Fri, 08 Feb 2019 04:24:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727555AbfBHMY5 (ORCPT + 31 others); Fri, 8 Feb 2019 07:24:57 -0500 Received: from mx.socionext.com ([202.248.49.38]:27736 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726547AbfBHMY4 (ORCPT ); Fri, 8 Feb 2019 07:24:56 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:24:54 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 09A79180D62; Fri, 8 Feb 2019 21:24:55 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:24:54 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 787901A04E1; Fri, 8 Feb 2019 21:24:54 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 640961202F1; Fri, 8 Feb 2019 21:24:54 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 01/15] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram Date: Fri, 8 Feb 2019 21:25:33 +0900 Message-Id: <1549628733-30171-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 0000000..194f6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + };