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[V8,5/9] EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.

Message ID 1364998113-13428-6-git-send-email-amarendra.xt@samsung.com
State Superseded
Headers show

Commit Message

Amar April 3, 2013, 2:08 p.m. UTC
This patch initialises the local variable 'shift' to zero.
The uninitialised local variable 'shift' had garbage value and was
resulting in unwnated results in the functions exynos5_get_mmc_clk()
and exynos4_get_mmc_clk().

Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes since V1:
	1)Updated the function exynos5_mmc_set_clk_div() to receive
	'device_i'd as input parameter instead of 'index'.

Changes since V2:
	1)Updation of commit message and resubmition of proper patch set.

Changes since V3:
	1)Removed the new API exynos5_mmc_set_clk_div() from clock.c,
	because existing API set_mmc_clk() can be used to set mmc clock.

Changes since V4:
	1)Updated the subject line to reflect the changes present in this patch.
	2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which
	were present in this patch, have been moved out of this patch.

Changes since V5:
	No change.

Changes since V6:
	No change.

Changes since V7:
	No change.

 arch/arm/cpu/armv7/exynos/clock.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Jaehoon Chung April 9, 2013, 10:54 a.m. UTC | #1
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 04/03/2013 11:08 PM, Amar wrote:
> This patch initialises the local variable 'shift' to zero.
> The uninitialised local variable 'shift' had garbage value and was
> resulting in unwnated results in the functions exynos5_get_mmc_clk()
> and exynos4_get_mmc_clk().
> 
> Signed-off-by: Amar <amarendra.xt@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> Changes since V1:
> 	1)Updated the function exynos5_mmc_set_clk_div() to receive
> 	'device_i'd as input parameter instead of 'index'.
> 
> Changes since V2:
> 	1)Updation of commit message and resubmition of proper patch set.
> 
> Changes since V3:
> 	1)Removed the new API exynos5_mmc_set_clk_div() from clock.c,
> 	because existing API set_mmc_clk() can be used to set mmc clock.
> 
> Changes since V4:
> 	1)Updated the subject line to reflect the changes present in this patch.
> 	2)Changes of the file arch/arm/include/asm/arch-exynos/clk.h which
> 	were present in this patch, have been moved out of this patch.
> 
> Changes since V5:
> 	No change.
> 
> Changes since V6:
> 	No change.
> 
> Changes since V7:
> 	No change.
> 
>  arch/arm/cpu/armv7/exynos/clock.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 223660a..cf3247a 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -613,7 +613,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
>  		(struct exynos4_clock *)samsung_get_base_clock();
>  	unsigned long uclk, sclk;
>  	unsigned int sel, ratio, pre_ratio;
> -	int shift;
> +	int shift = 0;
>  
>  	sel = readl(&clk->src_fsys);
>  	sel = (sel >> (dev_index << 2)) & 0xf;
> @@ -662,7 +662,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
>  		(struct exynos5_clock *)samsung_get_base_clock();
>  	unsigned long uclk, sclk;
>  	unsigned int sel, ratio, pre_ratio;
> -	int shift;
> +	int shift = 0;
>  
>  	sel = readl(&clk->src_fsys);
>  	sel = (sel >> (dev_index << 2)) & 0xf;
>
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 223660a..cf3247a 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -613,7 +613,7 @@  static unsigned long exynos4_get_mmc_clk(int dev_index)
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;
@@ -662,7 +662,7 @@  static unsigned long exynos5_get_mmc_clk(int dev_index)
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;