From patchwork Thu Feb 21 10:15:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 158893 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp309822jaa; Thu, 21 Feb 2019 02:18:54 -0800 (PST) X-Google-Smtp-Source: AHgI3IbOluDi3J1sIaAkHyzAf/23DmJ4EtEzX/fAkKqKu+//V4wVIN4/8VNk/cT1m0Yrvj40b6E6 X-Received: by 2002:a63:e051:: with SMTP id n17mr33752977pgj.258.1550744334158; Thu, 21 Feb 2019 02:18:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550744334; cv=none; d=google.com; s=arc-20160816; b=B9iC1moi4TpI/vUWY4k4L0DIj8n18dTARSr24mbIIu8FWJFsCwcj+EKPJoOFsaWP6e hp4q5RIv3UZ6ULo0iIqx85PMjo0yHQQGF1eVtEf9xXdKCLEnscPoa0gUw7wzgl5dLCBf WjqoCy8OKguGLWwNTAFWOVhax2rvi001nF6KcUuIemO4GMXtJc4nQnZAs/gSke8aZht5 RlOYcbwwAO7nJi6OuXpMV+i8A7LGEYrj6SymuE2wGnQ0hsXdBLCzghuLM2OcmxIyS9M8 wmI9ADuMftzsRBrLEoGBYZM8qMpnBQdBl6C5VjO7LlVbhqpUu+wcMlrntXpabFeU/Bjg TSAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=jj6FmrtAATey3jXJiSTKNFfft8ZueXEih9SzlA0HGn0=; b=hkBUUbdrvQrkGmWZ8BeWFBWrUUQzXKo5jMF6xc9K0sGcXl6tVBh6ixIuzLLOqfXIiZ 9J62TvTWe3eAAiZVD5XjHery/SSR3i/HCu8sQpmLX3+4aPIz7s2AA/kbaJEkHH24xRRT Dijly+aZWUJFQnUtmRY59qGrrh371zaP+f2eg/agk43UPA8KpazGbGzO7g8OeNtABVAD K6HMto/DyVAWc7UuprwkDWDwHN/18OsDPiLOJCPW6WQG8hIkkeI/Nev8pGTJDLaQu5wy IWKhLjfHr8UQZhCQu/jJkTJtVjuPv1ar19k6F+I7BCFZWP+FpqXPIFcX4LnA7FKds39b DeQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ulCxE0QS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r14si16631202pls.306.2019.02.21.02.18.53; Thu, 21 Feb 2019 02:18:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ulCxE0QS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727815AbfBUKSw (ORCPT + 32 others); Thu, 21 Feb 2019 05:18:52 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42110 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727785AbfBUKSu (ORCPT ); Thu, 21 Feb 2019 05:18:50 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1LAIdV2053151; Thu, 21 Feb 2019 04:18:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550744319; bh=jj6FmrtAATey3jXJiSTKNFfft8ZueXEih9SzlA0HGn0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ulCxE0QS++KfNd9ZaYoPlqNLYknNU4OzUSY4WPh+dB/PjGvg+c4PYTm1qB2ScdlvS Gvqj0gCIEc4qyAiysadySuT4lt2gmLdgEhxfHJJEsU0EGBDdwdYFBLnyzuECqVBEnL akcnr/oPSQbjuunEbtql9nYWKUTzWDMnaFJtPXtk= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1LAIdf8070437 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 Feb 2019 04:18:39 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 21 Feb 2019 04:18:38 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 21 Feb 2019 04:18:38 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1LAIORJ022198; Thu, 21 Feb 2019 04:18:36 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v4 4/9] PCI: keystone: Use hwirq to get the MSI IRQ number offset Date: Thu, 21 Feb 2019 15:45:13 +0530 Message-ID: <20190221101518.22604-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190221101518.22604-1-kishon@ti.com> References: <20190221101518.22604-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous. And this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 24 ++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 7f1648453f54..0ebb8622fddb 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -75,7 +75,6 @@ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define MAX_MSI_HOST_IRQS 8 /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -90,7 +89,7 @@ struct keystone_pcie { u32 device_id; struct device_node *legacy_intc_np; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int msi_host_irq; int num_lanes; u32 num_viewport; struct phy **phy; @@ -610,9 +609,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); + unsigned int irq = desc->irq_data.hwirq; struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - u32 offset = irq - ks_pcie->msi_host_irqs[0]; + u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -634,6 +633,7 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) struct device *dev = ks_pcie->pci->dev; struct device_node *np = ks_pcie->np; struct device_node *intc_np; + struct irq_data *irq_data; int irq_count, irq, ret, i; if (!IS_ENABLED(CONFIG_PCI_MSI)) @@ -652,19 +652,21 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) goto err; } - if (irq_count > MAX_MSI_HOST_IRQS) { - dev_warn(dev, "Too many MSI interrupt lines defined %u\n", - irq_count); - irq_count = MAX_MSI_HOST_IRQS; - } - for (i = 0; i < irq_count; i++) { irq = irq_of_parse_and_map(intc_np, i); if (!irq) { ret = -EINVAL; goto err; } - ks_pcie->msi_host_irqs[i] = irq; + + if (!ks_pcie->msi_host_irq) { + irq_data = irq_get_irq_data(irq); + if (!irq_data) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irq = irq_data->hwirq; + } irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, ks_pcie);