From patchwork Fri Apr 5 09:09:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 15939 Return-Path: X-Original-To: linaro@staging.patches.linaro.org Delivered-To: linaro@staging.patches.linaro.org Received: from mail-vc0-f199.google.com (mail-vc0-f199.google.com [209.85.220.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A7A4027763 for ; Fri, 5 Apr 2013 09:09:49 +0000 (UTC) Received: by mail-vc0-f199.google.com with SMTP id ha11sf5286472vcb.2 for ; Fri, 05 Apr 2013 02:09:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=EkXHuRdfdLU5xxPAbboYht6lrSeLDQk0bozr+RucQ48=; b=lNMoTKqHwFkgV2JKYgqoflLDoW+xrPNMdCB128pyyA14mmg82pyrlmULUhYqN6eLow wdEZsTPt6dinZtP+j+PcGvb69vtHlH7yBznUYSuCKVbepu9P10bUCerbiy6F+EdVHL4h 4NgbCGKBRTnxbS4+PB+pkg8mZOcV+SkCW0mhheD4CNbcEwkN4wIeyFXhoqg7hXK5bMQL CaKvF2lDRLyRBavgscOwZnJ91ZCwMEObKPyaLK/4y+sLDkL77Mh7+7cuQVbdz7hpDHU0 yWCHu/v+lR5/YW9Bt0drf46s1IiD5FYOQVaB0+xi+abg1jsq2ZPLkDUKDr6wIA+JiTKo SlLQ== X-Received: by 10.224.172.200 with SMTP id m8mr5080754qaz.0.1365152982168; Fri, 05 Apr 2013 02:09:42 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.99.74 with SMTP id eo10ls89576qeb.29.gmail; Fri, 05 Apr 2013 02:09:41 -0700 (PDT) X-Received: by 10.58.220.229 with SMTP id pz5mr7472219vec.30.1365152981897; Fri, 05 Apr 2013 02:09:41 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id d10si10491852vdv.106.2013.04.05.02.09.41 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Apr 2013 02:09:41 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id kw10so817046vcb.33 for ; Fri, 05 Apr 2013 02:09:41 -0700 (PDT) X-Received: by 10.58.238.65 with SMTP id vi1mr7498324vec.31.1365152981721; Fri, 05 Apr 2013 02:09:41 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.85.136 with SMTP id h8csp250315vez; Fri, 5 Apr 2013 02:09:41 -0700 (PDT) X-Received: by 10.68.213.231 with SMTP id nv7mr13779811pbc.85.1365152980782; Fri, 05 Apr 2013 02:09:40 -0700 (PDT) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx.google.com with ESMTPS id io9si13719462pbc.318.2013.04.05.02.09.40 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Apr 2013 02:09:40 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.54 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.160.54; Received: by mail-pb0-f54.google.com with SMTP id xa7so1918387pbc.13 for ; Fri, 05 Apr 2013 02:09:40 -0700 (PDT) X-Received: by 10.66.146.232 with SMTP id tf8mr14343610pab.32.1365152980131; Fri, 05 Apr 2013 02:09:40 -0700 (PDT) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id gj2sm13689644pbc.25.2013.04.05.02.09.36 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Apr 2013 02:09:39 -0700 (PDT) From: Inderpal Singh To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, promsoft@gmail.com, chander.kashyap@linaro.org, patches@linaro.org Subject: [PATCH v3 2/3] exynos: update tzpc to make it common for exynos4 and exynos5 Date: Fri, 5 Apr 2013 14:39:20 +0530 Message-Id: <1365152961-25760-3-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1365152961-25760-1-git-send-email-inderpal.singh@linaro.org> References: <1365152961-25760-1-git-send-email-inderpal.singh@linaro.org> X-Gm-Message-State: ALoCoQnz5mukhVz9Rxt+nnx8Vf2ZUOjuzBqb6aNgHmr9CJJxFchcTmAqa9OUENwtITLzHWNDk+bU X-Original-Sender: inderpal.singh@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh Acked-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/tzpc.c | 23 ++++++++++++++++------- arch/arm/cpu/armv7/s5p-common/Makefile | 2 ++ arch/arm/include/asm/arch-exynos/cpu.h | 4 ++++ arch/arm/include/asm/arch-exynos/tzpc.h | 14 +++----------- board/samsung/smdk5250/lowlevel_init.S | 2 ++ spl/Makefile | 4 ++++ 6 files changed, 31 insertions(+), 18 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/tzpc.c b/arch/arm/cpu/armv7/exynos/tzpc.c index 81adb4b..f5e8e9c 100644 --- a/arch/arm/cpu/armv7/exynos/tzpc.c +++ b/arch/arm/cpu/armv7/exynos/tzpc.c @@ -22,6 +22,7 @@ * MA 02111-1307 USA */ +#include #include #include @@ -29,20 +30,28 @@ void tzpc_init(void) { struct exynos_tzpc *tzpc; - unsigned int addr; + unsigned int addr, start = 0, end = 0; - for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { + start = samsung_get_base_tzpc(); + + if (cpu_is_exynos5()) + end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); + else if (cpu_is_exynos4()) + end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET); + + for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) { tzpc = (struct exynos_tzpc *)addr; - if (addr == TZPC0_BASE) + if (addr == start) writel(R0SIZE, &tzpc->r0size); writel(DECPROTXSET, &tzpc->decprot0set); writel(DECPROTXSET, &tzpc->decprot1set); - if (addr != TZPC9_BASE) { - writel(DECPROTXSET, &tzpc->decprot2set); - writel(DECPROTXSET, &tzpc->decprot3set); - } + if (cpu_is_exynos5() && (addr == end)) + break; + + writel(DECPROTXSET, &tzpc->decprot2set); + writel(DECPROTXSET, &tzpc->decprot3set); } } diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 1705399..0c38bd0 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -26,9 +26,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o +ifndef CONFIG_SPL_BUILD COBJS-y += timer.o COBJS-y += sromc.o COBJS-$(CONFIG_PWM) += pwm.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index f76e489..36b98c8 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -38,6 +38,7 @@ #define EXYNOS4_CLOCK_BASE 0x10030000 #define EXYNOS4_SYSTIMER_BASE 0x10050000 #define EXYNOS4_WATCHDOG_BASE 0x10060000 +#define EXYNOS4_TZPC_BASE 0x10110000 #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_DMC0_BASE 0x10400000 #define EXYNOS4_DMC1_BASE 0x10410000 @@ -74,6 +75,7 @@ #define EXYNOS4X12_CLOCK_BASE 0x10030000 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000 +#define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_DMC0_BASE 0x10600000 #define EXYNOS4X12_DMC1_BASE 0x10610000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 @@ -107,6 +109,7 @@ #define EXYNOS5_POWER_BASE 0x10040000 #define EXYNOS5_SWRESET 0x10040400 #define EXYNOS5_SYSREG_BASE 0x10050000 +#define EXYNOS5_TZPC_BASE 0x10100000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 @@ -233,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) SAMSUNG_BASE(spi, SPI_BASE) SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) +SAMSUNG_BASE(tzpc, TZPC_BASE) #endif #endif /* _EXYNOS4_CPU_H */ diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h index 050ad70..4d9c3a3 100644 --- a/arch/arm/include/asm/arch-exynos/tzpc.h +++ b/arch/arm/include/asm/arch-exynos/tzpc.h @@ -48,18 +48,10 @@ struct exynos_tzpc { unsigned int pcellid3; }; -/* TZPC : Register Offsets */ -#define TZPC0_BASE 0x10100000 -#define TZPC1_BASE 0x10110000 -#define TZPC2_BASE 0x10120000 -#define TZPC3_BASE 0x10130000 -#define TZPC4_BASE 0x10140000 -#define TZPC5_BASE 0x10150000 -#define TZPC6_BASE 0x10160000 -#define TZPC7_BASE 0x10170000 -#define TZPC8_BASE 0x10180000 -#define TZPC9_BASE 0x10190000 +#define EXYNOS4_NR_TZPC_BANKS 6 +#define EXYNOS5_NR_TZPC_BANKS 10 +/* TZPC : Register Offsets */ #define TZPC_BASE_OFFSET 0x10000 /* diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S index bc6cb6f..edc565e 100644 --- a/board/samsung/smdk5250/lowlevel_init.S +++ b/board/samsung/smdk5250/lowlevel_init.S @@ -75,12 +75,14 @@ lowlevel_init: bl mem_ctrl_init 1: + bl arch_cpu_init bl tzpc_init ldmia r13!, {ip,pc} wakeup_reset: bl system_clock_init bl mem_ctrl_init + bl arch_cpu_init bl tzpc_init exit_wakeup: diff --git a/spl/Makefile b/spl/Makefile index b5a8de7..cdbaa7f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -94,6 +94,10 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o endif +ifeq ($(SOC),exynos) +LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o +endif + # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o