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[209.132.180.67]) by mx.google.com with ESMTP id q22si10484983plr.384.2019.03.13.02.00.27; Wed, 13 Mar 2019 02:00:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=inRvYdF2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727305AbfCMJA0 (ORCPT + 7 others); Wed, 13 Mar 2019 05:00:26 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:41712 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727332AbfCMJAZ (ORCPT ); Wed, 13 Mar 2019 05:00:25 -0400 Received: by mail-lj1-f193.google.com with SMTP id z25so804271ljk.8 for ; Wed, 13 Mar 2019 02:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lRuCf454mnzXB+DyjyFfFPdMgMq/C5zdWzQg4oC5VkU=; b=inRvYdF2URJMHy6DjIr+GhGLMU3P1FzqcqtEDRK4JChuFpTLPGpOXtV+RO7/5dckAL jpeGejyWeb/QXvr0zUbCfzv5imaWuFE8wlhpWlFxqC8uX5ShsK5sWeKiHgO8TEXRm1kj mqT+DHt8hKej3THaZPN8rbwK1rMZYmYkyAGrcCnAMoqRxxNnJykTIdVW1fQYmKs7gZln +R0hIrYLWqWlsKlY0LeNuBvvrVJQKFJR6/+GH7XKRikBbsWDbg1AqOKFIRinz1/qSmVm WCvKsymK5Mv7aT4QBueq3B5eBZpjEXka9bfjlOqe7cbZPc4fU+Dto10G8lkRcRDJdQtd 6YGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lRuCf454mnzXB+DyjyFfFPdMgMq/C5zdWzQg4oC5VkU=; b=bHK63zOG2QQs/mEQdOSUY58AzT4WT9bTYk1nEIzXA27pqtVyB70d4VMPEnWejtwxGt gUm0SOubhH4NB1y66FWeiIOfmJuZqMLZ11/t1E1Igg948x5D3hjzlom4kNpUSTHYADwu HiPds3zt7zYMq58bI52Fki07B1HvN+ovEl1JhV5gtmkvZQ2vwCJyprZi1fGIDuZNE9/E efETWCsRExYD4QfeTrKRtYFrsOkAO7JSjmYeGk1yWzLpTp1VAz70vkAMy4yd2K6bIq5n QZTW2VEajN3iVIUJgXfB4sd6ZgySl+ErwvR5P42Io1wktbb0cRxNb5SkqZMN2NF6PI3p psqg== X-Gm-Message-State: APjAAAWJvTcR1x4n0Z0PDTrW5VEdtzs0Qt3UOd44D7BUAl06CoSEJyE4 +tWJsuaAZX3Al3Z3FeSNDoRGAg== X-Received: by 2002:a2e:8585:: with SMTP id b5mr22362278lji.125.1552467623334; Wed, 13 Mar 2019 02:00:23 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id u15sm1701986lja.73.2019.03.13.02.00.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Mar 2019 02:00:22 -0700 (PDT) From: Georgi Djakov To: vireshk@kernel.org, sboyd@kernel.org, nm@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net Cc: jcrouse@codeaurora.org, vincent.guittot@linaro.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, sibis@codeaurora.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH 4/4] cpufreq: dt: Add support for interconnect bandwidth scaling Date: Wed, 13 Mar 2019 11:00:10 +0200 Message-Id: <20190313090010.20534-5-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190313090010.20534-1-georgi.djakov@linaro.org> References: <20190313090010.20534-1-georgi.djakov@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In addition to clocks and regulators, some devices can scale the bandwidth of their on-chip interconnect - for example between CPU and DDR memory. Add support for that, so that platforms which support it can make use of it. Signed-off-by: Georgi Djakov --- drivers/cpufreq/cpufreq-dt.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c index e58bfcb1169e..30fed0fc266d 100644 --- a/drivers/cpufreq/cpufreq-dt.c +++ b/drivers/cpufreq/cpufreq-dt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +101,7 @@ static int resources_available(void) struct device *cpu_dev; struct regulator *cpu_reg; struct clk *cpu_clk; + struct icc_path *cpu_path; int ret = 0; const char *name; @@ -126,6 +128,19 @@ static int resources_available(void) clk_put(cpu_clk); + cpu_path = of_icc_get(cpu_dev, NULL); + ret = PTR_ERR_OR_ZERO(cpu_path); + if (ret) { + if (ret == -EPROBE_DEFER) + dev_dbg(cpu_dev, "defer icc path: %d\n", ret); + else + dev_err(cpu_dev, "failed to get icc path: %d\n", ret); + + return ret; + } + + icc_put(cpu_path); + name = find_supply_name(cpu_dev); /* Platform doesn't require regulator */ if (!name) @@ -205,10 +220,18 @@ static int cpufreq_init(struct cpufreq_policy *policy) } } + opp_table = dev_pm_opp_set_path(cpu_dev, NULL); + if (IS_ERR(opp_table)) { + ret = PTR_ERR(opp_table); + dev_err(cpu_dev, "Failed to set interconnect path for cpu%d: %d\n", + policy->cpu, ret); + goto out_put_regulator; + } + priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) { ret = -ENOMEM; - goto out_put_regulator; + goto out_put_path; } priv->reg_name = name; @@ -288,6 +311,8 @@ static int cpufreq_init(struct cpufreq_policy *policy) if (priv->have_static_opps) dev_pm_opp_of_cpumask_remove_table(policy->cpus); kfree(priv); +out_put_path: + dev_pm_opp_put_path(opp_table); out_put_regulator: if (name) dev_pm_opp_put_regulators(opp_table);