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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id h127si1137753pfb.213.2019.03.20.01.08.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:08:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=zQZHLP5h; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B726C211E0112; Wed, 20 Mar 2019 01:08:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::443; helo=mail-pf1-x443.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E5E0C211E0105 for ; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id v21so1328015pfm.12 for ; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nStjCkDwSvD7Acz71PF2JEFATBKIYWPp45M7q5OoJsA=; b=zQZHLP5hEL/aJ3fgvSfbZoQyWGxXMwKWTwDBEy3AgTGEMmySMKtEjQR6bXlpi0sEYX 5ieBr7gpR0lrJd2gMRbqinSGVQ83zScHVV1W7Bf+2Fm1SOH88QEMXoyMVtIaLJZffEJI 3dN6g5AsXRKT0pp5CsSBXQHykK4HWX+DSjUf9bpvxl9TVuGATFC5ibatqbFkM6mAEhj2 51ccv4+1QCLwx8MuzYt0KlJE0jFxJ5YBb0NRBKq8lDnnXhmCNnrKGVN8as4l0azKsKVj Ig8BGe+MubiIt/hy5Z94mtXfgfaQu03k5n2vGFGjg4SYU4r+8LgqJdr0Ep0+mQ9O2kPN RUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nStjCkDwSvD7Acz71PF2JEFATBKIYWPp45M7q5OoJsA=; b=TlWT/hyc8iQfjU/kMtJRauM1nC7Ad644T/FxS5I+aOZMssACMAI022i2Gv5vNYhhFG s91GZ0xQXhFawc757Qf0THqJXRAPZ6JBN05/ji0W1J9wYgwSRU70X2YrHatE21rMn6CP vMWoRf0bfezUZHnxegx8WOhs/IJ7GVCKzDBAD79xPSkMNO/+z8zUrtPLrxjwBdB2J4Pq 6JxqMG7E6j/jCeRE+bDZo2z0/wA2l+CzaYmn3+9yW4GCH/jD3ZfJeyAYWgpz+zNVoso7 xfl56wbrRNt6tmQDb3gkN30A4Amp76Hp65JIy31WUqu0kPLSR8JmAx48AQlpLcYlmLVl KL5A== X-Gm-Message-State: APjAAAXzX2TkprpW2wDQViQCf8Ww2pUdy+H7NRaGnTkugwZkNiFnOAEd Qk9NUHUTHNq6mRbopIev+URbCg== X-Received: by 2002:a17:902:be09:: with SMTP id r9mr7096801pls.189.1553069326283; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.08.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:08:45 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:12 +0800 Message-Id: <20190320080829.52003-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 01/18] Hisilicon/D0x: Remove and tidy some codes about SerdesLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As some definitions are about OemMiscLib, so move them from SerdesLib.h to OemMiscLib.h and drop some useless function definitions. After doing this, some unnecessary references can be removed for D03/D05. SerdesLib is useless for SmbiosMiscDxe and D06, so remove it and delete SerdesLib.h for D06. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/D06.dsc | 2 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 109 -------------------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 64 ------------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 --------------- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 ++++++++++++++ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 1 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- 11 files changed, 77 insertions(+), 266 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 396bd03c9d24..cbbd99e4a659 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -64,8 +64,6 @@ [LibraryClasses.common] CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf - SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 61cead7779b9..669e6a2d52cc 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -69,6 +69,7 @@ [LibraryClasses] BaseMemoryLib BaseLib DebugLib + OemMiscLib UefiBootServicesTableLib UefiRuntimeServicesTableLib UefiDriverEntryPoint @@ -77,7 +78,6 @@ [LibraryClasses] IpmiCmdLib - SerdesLib [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 077dd5edc847..b493dd9ac090 100755 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -16,116 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_ -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Sas0X8 = 2, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - -typedef enum { - Em32coreEvbBoard = 0, - Em16coreEvbBoard = 1, - EmV2R1CO5Borad = 2, - EmOtherBorad -} BOARD_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); - EFI_STATUS EfiSerdesInitWrap (VOID); -void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg); - -//EYE test -UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData); - -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - -//PRBS test -int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype); - -int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane); - -//CTLE/DFE -void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane); -//int serdes_reset(UINT32 macro); -//int serdes_release_reset(UINT32 macro); -void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode); -void serdes_ffe_show(UINT32 macro,UINT32 lane); -void serdes_dfe_show(UINT32 macro,UINT32 lane); -int serdes_read_bert(UINT8 macro, UINT8 lane); -void serdes_clean_bert(UINT8 macro, UINT8 lane); -int serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate); -void serdes_release_mcu(UINT32 macro,UINT32 val); -int hilink_write(UINT32 macro, UINT32 reg, UINT32 value); -int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value); -int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN -int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val); -int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val); -void serdes_ctle_show(UINT32 macro,UINT32 lane); -int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num); -int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num); -int report_serdes_mux(void); -int serdes_key_reg_show(UINT32 macro); -void serdes_state_show(UINT32 macro); -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - #endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h index 7ff924bd8954..b493dd9ac090 100644 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -16,71 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_ -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); -VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - EFI_STATUS EfiSerdesInitWrap (VOID); -INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro); #endif diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h deleted file mode 100644 index 05f0f7020e82..000000000000 --- a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType (UINT8 EthChannel); -VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - -EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode); -INT32 SerdesReset (UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro); -INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode); -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index 86ea6a1b3deb..b5a768856484 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,67 @@ #include #include +#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + +typedef enum { + EmHilink0Hccs1X8 = 0, + EmHilink0Pcie1X8 = 2, + EmHilink0Pcie1X4Pcie2X4 = 3, + EmHilink0Sas2X8 = 4, + EmHilink0Hccs1X8Width16, + EmHilink0Hccs1X8Width32, + EmHilink0Hccs1X8Speed5G, +} HILINK0_MODE_TYPE; + +typedef enum { + EmHilink1Sas2X1 = 0, + EmHilink1Hccs0X8 = 1, + EmHilink1Pcie0X8 = 2, + EmHilink1Hccs0X8Width16, + EmHilink1Hccs0X8Width32, + EmHilink1Hccs0X8Speed5G, +} HILINK1_MODE_TYPE; + +typedef enum { + EmHilink2Pcie2X8 = 0, + EmHilink2Hccs2X8 = 1, + EmHilink2Sas0X8 = 2, + EmHilink2Hccs2X8Width16, + EmHilink2Hccs2X8Width32, + EmHilink2Hccs2X8Speed5G, +} HILINK2_MODE_TYPE; + +typedef enum { + EmHilink5Pcie3X4 = 0, + EmHilink5Pcie2X2Pcie3X2 = 1, + EmHilink5Sas1X4 = 2, +} HILINK5_MODE_TYPE; + + +typedef struct { + HILINK0_MODE_TYPE Hilink0Mode; + HILINK1_MODE_TYPE Hilink1Mode; + HILINK2_MODE_TYPE Hilink2Mode; + UINT32 Hilink3Mode; + UINT32 Hilink4Mode; + HILINK5_MODE_TYPE Hilink5Mode; + UINT32 Hilink6Mode; + UINT32 UseSsc; +} SERDES_PARAM; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -53,4 +114,18 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID); extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); +UINTN OemGetCpuFreq (UINT8 Socket); + +UINTN +OemGetHccsFreq ( + VOID + ); + +EFI_STATUS +OemGetSerdesParam ( + SERDES_PARAM *ParamA, + SERDES_PARAM *ParamB, + UINT32 SocketId + ); + #endif diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 4771cb900c82..218b3540eb7f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -21,7 +21,6 @@ #include #include -#include #include #include diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c index ae4c194070e8..1a9ed620c80c 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -22,7 +22,6 @@ #include #include #include -#include #include diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c index 7e3f2e2a0e7d..c28ac6266fc6 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 2a9db46d1ff9..c5cb77696031 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index bc33639ac51d..945fd4c6e3c0 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -17,7 +17,7 @@ #include "SmbiosMisc.h" -#include +#include extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data; extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data;