[02/97] target/arm: Fix typo in do_sat_addsub_64

Message ID 20190401210011.16009-3-mdroth@linux.vnet.ibm.com
State New
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  • [01/97] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw
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Commit Message

Michael Roth April 1, 2019, 8:58 p.m.
From: Richard Henderson <richard.henderson@linaro.org>

Used the wrong temporary in the computation of subtractive overflow.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20180801123111.3595-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

(cherry picked from commit 7a31e0c6c68baffab0867bdd92b8744568b1d3ba)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

 target/arm/translate-sve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 374051cd20..9dd4c38bab 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1625,7 +1625,7 @@  static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
             /* Detect signed overflow for subtraction.  */
             tcg_gen_xor_i64(t0, reg, val);
             tcg_gen_sub_i64(t1, reg, val);
-            tcg_gen_xor_i64(reg, reg, t0);
+            tcg_gen_xor_i64(reg, reg, t1);
             tcg_gen_and_i64(t0, t0, reg);
             /* Bound the result.  */