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[209.132.180.67]) by mx.google.com with ESMTP id w189si27186481pgd.381.2019.04.15.03.44.08; Mon, 15 Apr 2019 03:44:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r0aQd45g; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727276AbfDOKoH (ORCPT + 15 others); Mon, 15 Apr 2019 06:44:07 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:43327 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727269AbfDOKoH (ORCPT ); Mon, 15 Apr 2019 06:44:07 -0400 Received: by mail-lj1-f194.google.com with SMTP id f18so15143585lja.10 for ; Mon, 15 Apr 2019 03:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mCjjQOD/ZfFecm9hHGoOQGAL+HEJt+HMGA/6wg4ncrc=; b=r0aQd45gX01nfBxag0dGNkt3R63i1s1+DXpD3VxantumGCcYcophA52d4ndhQJKI1i W2f7sQFEXVxu/EgQouyxWKJXat3pDbzUJV6Q6blSBfdNKIDRCMeqLzIO0tfP2LO+/q6Q cWRFHoAr2Dexy5lau0KkmCmi0VcNV2U79QG+Xwh16A+akc20R9dd5nbHgVXrq+yIHWNf OWKpH6G/mGxh/29xP3E7gJQRfdrgGW8s05lvXZnE7UyJh/Bl9zqfzcLeMTbrIlzwv+ay RuCndQCv3Qx/2+NyOW/+BxXC6RNo9wVJbGuNgiemUg4Fu38X01ojsgKo38O+LZpyycaE z6aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mCjjQOD/ZfFecm9hHGoOQGAL+HEJt+HMGA/6wg4ncrc=; b=rQXXKhRZBQ7r4orvBUGje2B2MG8Vv4IizD/SBx38piE2bFLwAHvGqMfxKBUbPtEWII OB/ZszWpr4eVXNIpJYNFIIgOdnUZvmFryP3BU9vHIPtS34fBw0rgdD+ubN5gQnbIeAB8 VXHVsz4uyVWw7KiBLKSqevJwcHJRhxv1VPdn79JwaUjdW/z+gY1iGkGoQJk/StCaFe3G 2v1ryGfpOLREhz0b/v1Lnzg7dgWY5OdcmgjmDQ2itYl8jF7afQNrhaH+S5XX2tmMMpb8 j8CHuoxu7WwAu1irmwzl9ocHUaXYyh9yU6AhukkOVXp7x8fZFxR2gyG8hDn04P5ywKXT NXFw== X-Gm-Message-State: APjAAAUGSdBKj/H3zA/BIaTYe1I1uS/i48Mqj8vpLDx8OB5JPJ5U+HqT MCE3SCpohracHRLIk5oeAFLnjg== X-Received: by 2002:a2e:86c7:: with SMTP id n7mr16016801ljj.44.1555325044913; Mon, 15 Apr 2019 03:44:04 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id k21sm9812596ljk.21.2019.04.15.03.44.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Apr 2019 03:44:04 -0700 (PDT) From: Georgi Djakov To: robh+dt@kernel.org, bjorn.andersson@linaro.org, georgi.djakov@linaro.org Cc: vkoul@kernel.org, evgreen@chromium.org, daidavid1@codeaurora.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: qcs404: Add interconnect provider DT nodes Date: Mon, 15 Apr 2019 13:43:56 +0300 Message-Id: <20190415104357.5305-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190415104357.5305-1-georgi.djakov@linaro.org> References: <20190415104357.5305-1-georgi.djakov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DT nodes for the network-on-chip interconnect buses found on qcs404-based platforms. Signed-off-by: Georgi Djakov --- v2: - No changes. arch/arm64/boot/dts/qcom/qcs404.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e8fd26633d57..706e918f79f6 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018, Linaro Limited +#include #include #include #include @@ -226,6 +227,30 @@ compatible = "qcom,rpm-qcs404"; qcom,glink-channels = "rpm_requests"; + bimc: interconnect@0 { + compatible = "qcom,qcs404-bimc"; + #interconnect-cells = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + pcnoc: interconnect@1 { + compatible = "qcom,qcs404-pcnoc"; + #interconnect-cells = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PNOC_CLK>, + <&rpmcc RPM_SMD_PNOC_A_CLK>; + }; + + snoc: interconnect@2 { + compatible = "qcom,qcs404-snoc"; + #interconnect-cells = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + rpmcc: clock-controller { compatible = "qcom,rpmcc-qcs404"; #clock-cells = <1>;