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[01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable

Message ID 20190416125744.27770-2-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Implement M profile floating point | expand

Commit Message

Peter Maydell April 16, 2019, 12:57 p.m. UTC 
Enforce that for M-profile various FPSCR bits which are RES0 there
but have defined meanings on A-profile are never settable. This
ensures that M-profile code can't enable the A-profile behaviour
(notably vector length/stride handling) by accident.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/vfp_helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

-- 
2.20.1

Comments

Richard Henderson April 23, 2019, 5:25 p.m. UTC | #1 
On 4/16/19 5:57 AM, Peter Maydell wrote:
> Enforce that for M-profile various FPSCR bits which are RES0 there

> but have defined meanings on A-profile are never settable. This

> ensures that M-profile code can't enable the A-profile behaviour

> (notably vector length/stride handling) by accident.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/vfp_helper.c | 8 ++++++++

>  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 2468fc16294..7a46d991486 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -105,6 +105,14 @@  void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
         val &= ~FPCR_FZ16;
     }
 
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        /*
+         * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
+         * and also for the trapped-exception-handling bits IxE.
+         */
+        val &= 0xf7c0009f;
+    }
+
     /*
      * We don't implement trapped exception handling, so the
      * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)