diff mbox series

[02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers

Message ID 20190416125744.27770-3-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Implement M profile floating point | expand

Commit Message

Peter Maydell April 16, 2019, 12:57 p.m. UTC 
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/intc/armv7m_nvic.c | 6 ++++++
 1 file changed, 6 insertions(+)

-- 
2.20.1

Comments

Richard Henderson April 23, 2019, 5:27 p.m. UTC | #1 
On 4/16/19 5:57 AM, Peter Maydell wrote:
> For M-profile the MVFR* ID registers are memory mapped, in the

> range we implement via the NVIC. Allow them to be read.

> (If the CPU has no FPU, these registers are defined to be RAZ.)

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  hw/intc/armv7m_nvic.c | 6 ++++++

>  1 file changed, 6 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ab822f42514..45d72f86bdf 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1222,6 +1222,12 @@  static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
             return 0;
         }
         return cpu->env.v7m.sfar;
+    case 0xf40: /* MVFR0 */
+        return cpu->isar.mvfr0;
+    case 0xf44: /* MVFR1 */
+        return cpu->isar.mvfr1;
+    case 0xf48: /* MVFR2 */
+        return cpu->isar.mvfr2;
     default:
     bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);