[25/38] target/xtensa: Use tcg_gen_abs_i32

Message ID	20190420073442.7488-26-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Fri, 19 Apr 2019 21:34:29 -1000 Message-Id: <20190420073442.7488-26-richard.henderson@linaro.org> In-Reply-To: <20190420073442.7488-1-richard.henderson@linaro.org> References: <20190420073442.7488-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 25/38] target/xtensa: Use tcg_gen_abs_i32 Precedence: list Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg vector improvements \| expand [00/38] tcg vector improvements [01/38] target/arm: Fill in .opc for cmtst_op [02/38] tcg: Assert fixed_reg is read-only [03/38] tcg: Return bool success from tcg_out_mov [04/38] tcg: Support cross-class moves without instruction support [05/38] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded [06/38] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface [07/38] tcg: Manually expand INDEX_op_dup_vec [08/38] tcg: Add tcg_out_dupm_vec to the backend interface [09/38] tcg/i386: Implement tcg_out_dupm_vec [10/38] tcg/aarch64: Implement tcg_out_dupm_vec [11/38] tcg: Add INDEX_op_dup_mem_vec [12/38] tcg: Add gvec expanders for variable shift [13/38] tcg/i386: Support vector variable shift opcodes [14/38] tcg/aarch64: Support vector variable shift opcodes [15/38] tcg: Implement tcg_gen_gvec_3i() [16/38] tcg: Specify optional vector requirements with a list [17/38] tcg: Add gvec expanders for vector shift by scalar [18/38] tcg/i386: Support vector scalar shift opcodes [19/38] tcg: Add support for integer absolute value [20/38] tcg: Add support for vector absolute value [21/38] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs [22/38] target/cris: Use tcg_gen_abs_tl [23/38] target/ppc: Use tcg_gen_abs_tl [24/38] target/s390x: Use tcg_gen_abs_i64 [25/38] target/xtensa: Use tcg_gen_abs_i32 [26/38] tcg/i386: Support vector absolute value [27/38] tcg/aarch64: Support vector absolute value [28/38] tcg: Add support for vector comparison select [29/38] tcg/i386: Support vector comparison select value [30/38] tcg/aarch64: Support vector comparison select value [31/38] target/ppc: Use vector variable shifts for VS{L, R, RA}{B, H, W, D} [32/38] target/arm: Vectorize USHL and SSHL [33/38] tcg/aarch64: Do not advertise minmax for MO_64 [34/38] tcg: Do not recreate INDEX_op_neg_vec unless supported [35/38] tcg: Introduce do_op3_nofail for vector expansion [36/38] tcg: Expand vector minmax using cmp+cmpsel [37/38] tcg/aarch64: Use MVNI for expansion of dupi [38/38] tcg/aarch64: Use ORRI and BICI for vector logical operations

Message ID

20190420073442.7488-26-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	209.51.188.17 as permitted sender) client-ip=209.51.188.17; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 19 Apr 2019 21:34:29 -1000
Message-Id: <20190420073442.7488-26-richard.henderson@linaro.org>
In-Reply-To: <20190420073442.7488-1-richard.henderson@linaro.org>
References: <20190420073442.7488-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH 25/38] target/xtensa: Use tcg_gen_abs_i32
Precedence: list
Cc: david@redhat.com
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

tcg vector improvements | expand

Comments

Philippe Mathieu-Daudé April 23, 2019, 10:14 p.m. UTC | #1

On 4/20/19 9:34 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/xtensa/translate.c | 9 +--------

>  1 file changed, 1 insertion(+), 8 deletions(-)

> 

> diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c

> index 65561d2c49..62be8a6f6a 100644

> --- a/target/xtensa/translate.c

> +++ b/target/xtensa/translate.c

> @@ -1707,14 +1707,7 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,

>  static void translate_abs(DisasContext *dc, const OpcodeArg arg[],

>                            const uint32_t par[])

>  {

> -    TCGv_i32 zero = tcg_const_i32(0);

> -    TCGv_i32 neg = tcg_temp_new_i32();

> -

> -    tcg_gen_neg_i32(neg, arg[1].in);

> -    tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out,

> -                        arg[1].in, zero, arg[1].in, neg);

> -    tcg_temp_free(neg);

> -    tcg_temp_free(zero);

> +    tcg_gen_abs_i32(arg[0].out, arg[1].in);

>  }

>  

>  static void translate_add(DisasContext *dc, const OpcodeArg arg[],

> 


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 65561d2c49..62be8a6f6a 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1707,14 +1707,7 @@  void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
 static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
                           const uint32_t par[])
 {
-    TCGv_i32 zero = tcg_const_i32(0);
-    TCGv_i32 neg = tcg_temp_new_i32();
-
-    tcg_gen_neg_i32(neg, arg[1].in);
-    tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out,
-                        arg[1].in, zero, arg[1].in, neg);
-    tcg_temp_free(neg);
-    tcg_temp_free(zero);
+    tcg_gen_abs_i32(arg[0].out, arg[1].in);
 }
 
 static void translate_add(DisasContext *dc, const OpcodeArg arg[],

[25/38] target/xtensa: Use tcg_gen_abs_i32

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