From patchwork Mon Apr 22 16:49:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 162612 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2801415jan; Mon, 22 Apr 2019 09:51:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqyfY7XUXFqv0q0jqBVH5OzDlIUKsqejEMta1+6/s8kpZamqQzAuBnjuHp8ualApgc8fIJPN X-Received: by 2002:a0d:e844:: with SMTP id r65mr10360591ywe.41.1555951883023; Mon, 22 Apr 2019 09:51:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555951883; cv=none; d=google.com; s=arc-20160816; b=oJRbKbZCOOkcr9j8+MPvLCDb9TmMkqcK0KOuRl6bxgmvcPjm3gT9RnIwmR2tHxdzdt 7eFPQYiJVglpfh83ZJRgcCUeQaXRNqvior8hB39ih6nzlM/vl/P3uRe7uFS89To4kfF2 QfdzBg2kmt6kl58ctRMotQY9o2CwUnQCxwm7EdX7L7YEvXM7CE09TUSIKNTOKqorHlVy YRmnzwce0NxxFS+38C6K4L5+DzQlanA3naqN/ix4YcEuaVrPlUxFlz8a7yz9qtNt2zjg jMo1QtlFpXkolI80I61tZAK+oK+kBTyirDXvpJAUGC52BRJ8vz6+mmgscxseyrLm7VO2 ekHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=QW/tjoOtb2n65Pv8Rs/tPaEWHScIZdDEAy+wzET2CsY=; b=LWyfbH9J1RQuAzjEVJbmhbtWbj0ihSC49Z/uwvrYYfF/6//q7Pldf/hsqL7ne7nUPs Kp4tHEuqMvaNP0srqLlaAWkWBmYA7vb4t61l1wwljJ6QNIHSlCrrnaaqXUGspMFCxBdQ wLLsd+YlH3soy/zHZ46RXrPwqbtI5UDuY/7SbsMQRvZmsrHKdjZVJ86Wmd51w7fa6pIE Pdx2yg+3SC8xPRCbyv70bFm1LuEZM+RKmfTKuSDXbGHtEyB39leVj25TPZ2LV1NGluzk jhMo5S+PKt80vQz0c17SM6xmOCARP8PnK8KLuwc0K4n/d25m0Cr9zwSFCOKZ/O12g2Eo 9Ngg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s8si8534038ybk.195.2019.04.22.09.51.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Apr 2019 09:51:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hIc8l-0004Sc-HZ; Mon, 22 Apr 2019 16:49:59 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hIc8k-0004RR-Co for xen-devel@lists.xenproject.org; Mon, 22 Apr 2019 16:49:58 +0000 X-Inumbo-ID: a8dcf381-651e-11e9-92d7-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id a8dcf381-651e-11e9-92d7-bc764e045a96; Mon, 22 Apr 2019 16:49:56 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AAE74EBD; Mon, 22 Apr 2019 09:49:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B6353F557; Mon, 22 Apr 2019 09:49:55 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 22 Apr 2019 17:49:21 +0100 Message-Id: <20190422164937.21350-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190422164937.21350-1-julien.grall@arm.com> References: <20190422164937.21350-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 04/20] xen/arm: Rework HSCTLR_BASE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , sstabellini@kernel.org, Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing ARMv8.4-LSE. Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is also not correct and looks like to be a verbatim copy from Arm32. HSCTLR_BASE is replaced with a bunch of per-architecture new defines helping to understand better what is the initialie value for SCTLR_EL2/HSCTLR. Note the defines *_CLEAR are only used to check the state of each bits are known. Lastly, the documentation is dropped from arm{32,64}/head.S as it would be pretty easy to get out-of-sync with the definitions. Signed-off-by: Julien Grall --- xen/arch/arm/arm32/head.S | 12 +--------- xen/arch/arm/arm64/head.S | 10 +------- xen/include/asm-arm/processor.h | 52 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 53 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 5ef7e5a2f3..8a98607459 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -234,17 +234,7 @@ cpu_init_done: ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* - * Set up the HSCTLR: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking enabled, - * MMU translation disabled (for now). - */ - ldr r0, =(HSCTLR_BASE|SCTLR_AXX_A) + ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) /* diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8a6be3352e..4fe904c51d 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -363,15 +363,7 @@ skip_bss: msr tcr_el2, x0 - /* Set up the SCTLR_EL2: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking disabled, - * MMU translation disabled (for now). */ - ldr x0, =(HSCTLR_BASE) + ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 /* Ensure that any exceptions encountered at EL2 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 1a143fb6a3..6dac500e40 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -122,6 +122,9 @@ #define SCTLR_A32_ELx_TE _BITUL(30) #define SCTLR_A32_ELx_FI _BITUL(21) +/* Common bits for SCTLR_ELx for Arm64 */ +#define SCTLR_A64_ELx_SA _BITUL(3) + /* Common bits for SCTLR_ELx on all architectures */ #define SCTLR_Axx_ELx_EE _BITUL(25) #define SCTLR_Axx_ELx_WXN _BITUL(19) @@ -130,7 +133,54 @@ #define SCTLR_Axx_ELx_A _BITUL(1) #define SCTLR_Axx_ELx_M _BITUL(0) -#define HSCTLR_BASE _AC(0x30c51878,U) +#ifdef CONFIG_ARM_32 + +#define HSCTLR_RES1 (_BITUL(3) | _BITUL(4) | _BITUL(5) | _BITUL(6) |\ + _BITUL(11) | _BITUL(16) | _BITUL(18) | _BITUL(22) |\ + _BITUL(23) | _BITUL(28) | _BITUL(29)) + +#define HSCTLR_RES0 (_BITUL(7) | _BITUL(8) | _BITUL(9) | _BITUL(10) |\ + _BITUL(13) | _BITUL(14) | _BITUL(15) | _BITUL(17) |\ + _BITUL(20) | _BITUL(24) | _BITUL(26) | _BITUL(27) |\ + _BITUL(31)) + +/* Initial value for HSCTLR */ +#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I) + +#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\ + SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\ + SCTLR_A32_ELx_TE) + +#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU +#error "Inconsistent HSCTLR set/clear bits" +#endif + +#else + +#define SCTLR_EL2_RES1 (_BITUL(4) | _BITUL(5) | _BITUL(11) | _BITUL(16) |\ + _BITUL(18) | _BITUL(22) | _BITUL(23) | _BITUL(28) |\ + _BITUL(29)) + +#define SCTLR_EL2_RES0 (_BITUL(6) | _BITUL(7) | _BITUL(8) | _BITUL(9) |\ + _BITUL(10) | _BITUL(13) | _BITUL(14) | _BITUL(15) |\ + _BITUL(17) | _BITUL(20) | _BITUL(21) | _BITUL(24) |\ + _BITUL(26) | _BITUL(27) | _BITUL(30) | _BITUL(31) |\ + (0xffffffffULL << 32)) + +/* Initial value for SCTLR_EL2 */ +#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\ + SCTLR_Axx_ELx_I) + +#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\ + SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE) + +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif + +#endif /* HCR Hyp Configuration Register */ #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */