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[209.132.180.67]) by mx.google.com with ESMTP id w3si22229688plp.260.2019.04.25.03.20.28; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rSPNLktu; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726855AbfDYKU2 (ORCPT + 5 others); Thu, 25 Apr 2019 06:20:28 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35946 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfDYKU2 (ORCPT ); Thu, 25 Apr 2019 06:20:28 -0400 Received: by mail-wr1-f65.google.com with SMTP id b1so18183698wru.3 for ; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/iI7nJ73SLpzt1a6DM6iMbKuntjQ5I6wTyzYnyQXX5c=; b=rSPNLktuJUWLr5ogZiBx00ruj9atfIW58tOa2byzuHAiY5SeG8rphCoi0i4uOG6UFP 694PwquuI9UCQRjzomAS4j6fbICBc9rskc8sdbG4NpXke8v3opzQfOu85VVebTyAOxz9 kPHlH+l6jYaBlBA0YTEyjvv3ya1RlvVxTPXapT8BKbseqbG2oiglJIGy87ZT2qhDr0M/ XF61Uz6d6rl13ObhK4cgrCz7ttjNFA+4TvFIBy34teVW0Vl/oL5QmjgBS/Co5aJXz42S Ysv60Ad2wxfB9v40d4LvoUMKvHvCqBvH6XJI/Hc53N8IEXo+0Po2P8VGfjmCKinZp/0K wUBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/iI7nJ73SLpzt1a6DM6iMbKuntjQ5I6wTyzYnyQXX5c=; b=qTG3cQUN9G3KeYg18+CKGp0LGNPa6wFizuge2QT3oupCO8V4vyjKgomWGa9MEIKvu/ HTUusN+0WDidkm1me5/bCKQ/OxAzpXLQtn9QbOai6rDHj7yFmdqjyUfZZGEQE65WKwRp /4QauRJnh039KJhmISmCcNW2/C/8xy0Uxo1sUg4o5pEl9A1ItBJrMg5MfaBmIn+cj41b C7xQpUjM3IBp30RId+SroknKjnHrw6QZ+A3asD9xed65gEDD9Xhf4wEM0yjBmc1hHdPG axWMVI+GvXCbeKNVEj2HHYKiT/XA1XNdOp1f5q/nbWF7wpef9TdadBYYxqptjSIonAIr esNw== X-Gm-Message-State: APjAAAU+z2uXH3Y0D9h0ycHFhIO4SVCsLqzxLnxocpZyRV12dU+U+VYS B035FfIXaIwTrOQntpuf53A1hg== X-Received: by 2002:adf:fb0d:: with SMTP id c13mr6697537wrr.214.1556187625771; Thu, 25 Apr 2019 03:20:25 -0700 (PDT) Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id p18sm5611364wrp.38.2019.04.25.03.20.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:20:24 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Ard Biesheuvel , Masahisa Kojima , Linus Walleij , Marc Zyngier , Graeme Gregory Subject: [RFC PATCH 2/3] irqchip/exiu: implement ACPI gpiolib/irqchip support Date: Thu, 25 Apr 2019 12:20:19 +0200 Message-Id: <20190425102020.21533-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Expose the existing EXIU hierarchical irqchip domain code to permit the interrupt controller to be used as the irqchip component of a GPIO controller on ACPI systems. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-sni-exiu.c | 82 +++++++++++++++++--- 1 file changed, 73 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index 52ce662334d4..99351cf997d9 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include @@ -134,9 +136,13 @@ static int exiu_domain_translate(struct irq_domain *domain, *hwirq = fwspec->param[1] - info->spi_base; *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - return 0; + } else { + if (fwspec->param_count != 2) + return -EINVAL; + *hwirq = fwspec->param[0]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; } - return -EINVAL; + return 0; } static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, @@ -147,16 +153,23 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; - if (fwspec->param_count != 3) - return -EINVAL; /* Not GIC compliant */ - if (fwspec->param[0] != GIC_SPI) - return -EINVAL; /* No PPI should point to this domain */ - + parent_fwspec = *fwspec; + if (is_of_node(dom->parent->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1] - info->spi_base; + } else if (is_fwnode_irqchip(dom->parent->fwnode)) { + hwirq = fwspec->param[0]; + parent_fwspec.param[0] = hwirq + info->spi_base + 32; + } else { + return -EINVAL; + } WARN_ON(nr_irqs != 1); - hwirq = fwspec->param[1] - info->spi_base; irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); - parent_fwspec = *fwspec; parent_fwspec.fwnode = dom->parent->fwnode; return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); } @@ -244,3 +257,54 @@ static int __init exiu_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init); + +#ifdef CONFIG_ACPI +static int exiu_acpi_gpio_to_irq(struct gpio_chip *gc, u32 gpio) +{ + struct irq_fwspec fwspec; + + fwspec.fwnode = gc->parent->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = gpio; + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; + + return irq_create_fwspec_mapping(&fwspec); +} + +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc) +{ + struct irq_domain *parent_domain = NULL, *domain; + struct resource *res; + int irq; + + irq = platform_get_irq(pdev, 0); + if (irq > 0) + parent_domain = irq_get_irq_data(irq)->domain; + + if (!parent_domain) { + dev_err(&pdev->dev, "unable to obtain parent domain\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "failed to parse memory resource\n"); + return -ENXIO; + } + + domain = exiu_init(parent_domain, dev_fwnode(&pdev->dev), res); + if (IS_ERR(domain)) { + dev_err(&pdev->dev, "failed to create IRQ domain (%ld)\n", + PTR_ERR(domain)); + return PTR_ERR(domain); + } + + gc->irq.domain = domain; + gc->to_irq = exiu_acpi_gpio_to_irq; + + dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS); + + return 0; +} +EXPORT_SYMBOL(exiu_acpi_init); +#endif