[PULL,23/31] tcg/aarch64: Support vector absolute value

Message ID	20190514000540.4313-24-richard.henderson@linaro.org
State	Accepted
Commit	a456394ae540f852cd0d10fd693fe9f33598dc01
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Mon, 13 May 2019 17:05:32 -0700 Message-Id: <20190514000540.4313-24-richard.henderson@linaro.org> In-Reply-To: <20190514000540.4313-1-richard.henderson@linaro.org> References: <20190514000540.4313-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 23/31] tcg/aarch64: Support vector absolute value Precedence: list Cc: peter.maydell@linux.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg: gvec improvments \| expand [PULL,00/31] tcg: gvec improvments [PULL,01/31] tcg: Implement tcg_gen_gvec_3i() [PULL,02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported [PULL,03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded [PULL,04/31] tcg: Specify optional vector requirements with a list [PULL,05/31] tcg: Assert fixed_reg is read-only [PULL,06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov [PULL,07/31] tcg: Return bool success from tcg_out_mov [PULL,08/31] tcg: Support cross-class moves without instruction support [PULL,09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface [PULL,10/31] tcg: Manually expand INDEX_op_dup_vec [PULL,11/31] tcg: Add tcg_out_dupm_vec to the backend interface [PULL,12/31] tcg/i386: Implement tcg_out_dupm_vec [PULL,13/31] tcg/aarch64: Implement tcg_out_dupm_vec [PULL,14/31] tcg: Add INDEX_op_dupm_vec [PULL,15/31] tcg: Add gvec expanders for variable shift [PULL,16/31] tcg/i386: Support vector variable shift opcodes [PULL,17/31] tcg/aarch64: Support vector variable shift opcodes [PULL,18/31] tcg: Add gvec expanders for vector shift by scalar [PULL,19/31] tcg/i386: Support vector scalar shift opcodes [PULL,20/31] tcg: Add support for integer absolute value [PULL,21/31] tcg: Add support for vector absolute value [PULL,22/31] tcg/i386: Support vector absolute value [PULL,23/31] tcg/aarch64: Support vector absolute value [PULL,24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs [PULL,25/31] target/cris: Use tcg_gen_abs_tl [PULL,26/31] target/ppc: Use tcg_gen_abs_i32 [PULL,27/31] target/ppc: Use tcg_gen_abs_tl [PULL,28/31] target/s390x: Use tcg_gen_abs_i64 [PULL,29/31] target/tricore: Use tcg_gen_abs_tl [PULL,30/31] target/xtensa: Use tcg_gen_abs_i32 [PULL,31/31] tcg/aarch64: Do not advertise minmax for MO_64

Message ID

20190514000540.4313-24-richard.henderson@linaro.org

State

Accepted

Commit

a456394ae540f852cd0d10fd693fe9f33598dc01

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 13 May 2019 17:05:32 -0700
Message-Id: <20190514000540.4313-24-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PULL 23/31] tcg/aarch64: Support vector absolute value
Precedence: list
Cc: peter.maydell@linux.org
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Series

tcg: gvec improvments | expand

Commit Message

Richard Henderson May 14, 2019, 12:05 a.m. UTC

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/aarch64/tcg-target.h     | 2 +-
 tcg/aarch64/tcg-target.inc.c | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

-- 
2.17.1

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 21d06d928c..e43554c3c7 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -132,7 +132,7 @@  typedef enum {
 #define TCG_TARGET_HAS_orc_vec          1
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          1
-#define TCG_TARGET_HAS_abs_vec          0
+#define TCG_TARGET_HAS_abs_vec          1
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index df123c07f1..1248dfd04c 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -552,6 +552,7 @@  typedef enum {
     I3617_CMGE0     = 0x2e208800,
     I3617_CMLE0     = 0x2e20a800,
     I3617_NOT       = 0x2e205800,
+    I3617_ABS       = 0x0e20b800,
     I3617_NEG       = 0x2e20b800,
 
     /* System instructions.  */
@@ -2208,6 +2209,9 @@  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_neg_vec:
         tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
         break;
+    case INDEX_op_abs_vec:
+        tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
+        break;
     case INDEX_op_and_vec:
         tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
         break;
@@ -2319,6 +2323,7 @@  int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_andc_vec:
     case INDEX_op_orc_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_abs_vec:
     case INDEX_op_not_vec:
     case INDEX_op_cmp_vec:
     case INDEX_op_shli_vec:
@@ -2562,6 +2567,7 @@  static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
         return &w_w_w;
     case INDEX_op_not_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_abs_vec:
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:

[PULL,23/31] tcg/aarch64: Support vector absolute value

Commit Message

Patch