diff mbox series

[1/2,PR88836,aarch64] Set CC_REGNUM instead of clobber

Message ID 1557972484-24599-2-git-send-email-kugan.vivekanandarajah@linaro.org
State New
Headers show
Series Fix redundant ptest instruction | expand

Commit Message

Kugan Vivekanandarajah May 16, 2019, 2:08 a.m. UTC 
From: Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>


For aarch64 sve while_ult pattern, Set CC_REGNUM instead of clobbering.

gcc/ChangeLog:

2019-05-16  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

	PR target/88834
	* config/aarch64/aarch64-sve.md (while_ult): Set CC_REGNUM instead
	of clobbering.

Change-Id: I96f16b8f81140fb4a6897d31d427c62bcc1e7997
---
 gcc/config/aarch64/aarch64-sve.md | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

-- 
2.7.4
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 3f39c4c..a18eb80 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1331,13 +1331,18 @@ 
 )
 
 ;; Set element I of the result if operand1 + J < operand2 for all J in [0, I].
-;; with the comparison being unsigned.
+;; with the comparison being unsigned. Als set CC_REFNUM with the flags.
 (define_insn "while_ult<GPI:mode><PRED_ALL:mode>"
   [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
 	(unspec:PRED_ALL [(match_operand:GPI 1 "aarch64_reg_or_zero" "rZ")
 			  (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")]
 			 UNSPEC_WHILE_LO))
-   (clobber (reg:CC CC_REGNUM))]
+   (set (reg:CC CC_REGNUM)
+	(compare:CC
+	  (unspec:SI [(vec_duplicate:PRED_ALL (const_int 1))
+		      (match_dup 0)]
+		     UNSPEC_PTEST_PTRUE)
+	  (const_int 0)))]
   "TARGET_SVE"
   "whilelo\t%0.<PRED_ALL:Vetype>, %<w>1, %<w>2"
 )