Message ID | 20190606174609.20487-6-peter.maydell@linaro.org |
---|---|
State | Superseded |
Headers | show
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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id z135sm2596784wmc.45.2019.06.06.10.46.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jun 2019 10:46:16 -0700 (PDT) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:32 +0100 Message-Id: <20190606174609.20487-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Richard Henderson <richard.henderson@linaro.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
target/arm: Convert VFP decoder to decodetree
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expand
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On 6/6/19 12:45 PM, Peter Maydell wrote: > At the moment our -cpu max for AArch32 supports VFP short-vectors > because we always implement them, even for CPUs which should > not have them. The following commits are going to switch to > using the correct ID-register-check to enable or disable short > vector support, so we need to turn it on explicitly for -cpu max, > because Cortex-A15 doesn't implement it. > > We don't enable this for the AArch64 -cpu max, because the v8A > architecture never supports short-vectors. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 044c4dd738b..3f06f6d1a20 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2022,6 +2022,10 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set (all of) the ID registers to
At the moment our -cpu max for AArch32 supports VFP short-vectors because we always implement them, even for CPUs which should not have them. The following commits are going to switch to using the correct ID-register-check to enable or disable short vector support, so we need to turn it on explicitly for -cpu max, because Cortex-A15 doesn't implement it. We don't enable this for the AArch64 -cpu max, because the v8A architecture never supports short-vectors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1