[PULL,04/48] hw/arm/smmuv3: Fix decoding of ID register range

Message ID 20190613121433.5246-5-peter.maydell@linaro.org
State Accepted
Commit 97fb318d37be4d21125e89c96e4e92ea33beac51
Headers show
Series
  • target-arm queue
Related show

Commit Message

Peter Maydell June 13, 2019, 12:13 p.m.
The SMMUv3 ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Message-id: 20190524124829.2589-1-peter.maydell@linaro.org
---
 hw/arm/smmuv3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.20.1

Patch

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index fd8ec7860ee..e96d5beb9a8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1232,7 +1232,7 @@  static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
                               uint64_t *data, MemTxAttrs attrs)
 {
     switch (offset) {
-    case A_IDREGS ... A_IDREGS + 0x1f:
+    case A_IDREGS ... A_IDREGS + 0x2f:
         *data = smmuv3_idreg(offset - A_IDREGS);
         return MEMTX_OK;
     case A_IDR0 ... A_IDR5: