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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y6sm2010576wrp.12.2019.06.13.05.14.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 05:14:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 13 Jun 2019 13:14:00 +0100 Message-Id: <20190613121433.5246-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190613121433.5246-1-peter.maydell@linaro.org> References: <20190613121433.5246-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree. trans_VCVT() is temporarily left in translate.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 72 +++++++++++++++++------------------- target/arm/vfp-uncond.decode | 6 +++ 2 files changed, 39 insertions(+), 39 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1da683820ab..d59fadc8fbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3340,12 +3340,31 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return true; } -static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, - int rounding) +static bool trans_VCVT(DisasContext *s, arg_VCVT *a) { - bool is_signed = extract32(insn, 7, 1); - TCGv_ptr fpst = get_fpstatus_ptr(0); + uint32_t rd, rm; + bool dp = a->dp; + TCGv_ptr fpst; TCGv_i32 tcg_rmode, tcg_shift; + int rounding = fp_decode_rm[a->rm]; + bool is_signed = a->op; + + if (!dc_isar_feature(aa32_vcvt_dr, s)) { + return false; + } + + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + return false; + } + rd = a->vd; + rm = a->vm; + + if (!vfp_access_check(s)) { + return true; + } + + fpst = get_fpstatus_ptr(0); tcg_shift = tcg_const_i32(0); @@ -3355,10 +3374,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, if (dp) { TCGv_i64 tcg_double, tcg_res; TCGv_i32 tcg_tmp; - /* Rd is encoded as a single precision register even when the source - * is double precision. - */ - rd = ((rd << 1) & 0x1e) | ((rd >> 4) & 0x1); tcg_double = tcg_temp_new_i64(); tcg_res = tcg_temp_new_i64(); tcg_tmp = tcg_temp_new_i32(); @@ -3395,28 +3410,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, tcg_temp_free_ptr(fpst); - return 0; -} - -static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn) -{ - uint32_t rd, rm, dp = extract32(insn, 8, 1); - - if (dp) { - VFP_DREG_D(rd, insn); - VFP_DREG_M(rm, insn); - } else { - rd = VFP_SREG_D(insn); - rm = VFP_SREG_M(insn); - } - - if ((insn & 0x0fbc0e50) == 0x0ebc0a40 && - dc_isar_feature(aa32_vcvt_dr, s)) { - /* VCVTA, VCVTN, VCVTP, VCVTM */ - int rounding = fp_decode_rm[extract32(insn, 16, 2)]; - return handle_vcvt(insn, rd, rm, dp, rounding); - } - return 1; + return true; } /* @@ -3452,6 +3446,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } + if (extract32(insn, 28, 4) == 0xf) { + /* + * Encodings with T=1 (Thumb) or unconditional (ARM): these + * were all handled by the decodetree decoder, so any insn + * patterns which get here must be UNDEF. + */ + return 1; + } + /* * FIXME: this access check should not take precedence over UNDEF * for invalid encodings; we will generate incorrect syndrome information @@ -3468,15 +3471,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 0; } - if (extract32(insn, 28, 4) == 0xf) { - /* - * Encodings with T=1 (Thumb) or unconditional (ARM): - * only used for the "miscellaneous VFP features" added in v8A - * and v7M (and gated on the MVFR2.FPMisc field). - */ - return disas_vfp_misc_insn(s, insn); - } - dp = ((insn & 0xf00) == 0xb00); switch ((insn >> 24) & 0xf) { case 0xe: diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 0aa83285de2..5af1f2ee664 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -55,3 +55,9 @@ VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ vm=%vm_sp vd=%vd_sp dp=0 VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ vm=%vm_dp vd=%vd_dp dp=1 + +# VCVT float to int with specified rounding mode; Vd is always single-precision +VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ + vm=%vm_sp vd=%vd_sp dp=0 +VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ + vm=%vm_dp vd=%vd_sp dp=1