[RISU] arm.risu: Avoid VTRN with Vd == Vm

Message ID 20190613143741.15128-1-peter.maydell@linaro.org
State Accepted
Headers show
Series
  • [RISU] arm.risu: Avoid VTRN with Vd == Vm
Related show

Commit Message

Peter Maydell June 13, 2019, 2:37 p.m.
The AArch32 VTRN instruction is specified to give an UNKNOWN
result if Vd and Vm are the same register; avoid generating
this in risu output, as we already do for VUZP and VZIP.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
Alex: this pattern error is why we don't pass your
testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared
with a real Cortex-A7. You probably want to update that.

 arm.risu | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.20.1

Comments

Richard Henderson June 13, 2019, 9:17 p.m. | #1
On 6/13/19 7:37 AM, Peter Maydell wrote:
> The AArch32 VTRN instruction is specified to give an UNKNOWN

> result if Vd and Vm are the same register; avoid generating

> this in risu output, as we already do for VUZP and VZIP.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

> Alex: this pattern error is why we don't pass your

> testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared

> with a real Cortex-A7. You probably want to update that.

> 

>  arm.risu | 3 ++-

>  1 file changed, 2 insertions(+), 1 deletion(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
Peter Maydell June 17, 2019, 2:24 p.m. | #2
On Thu, 13 Jun 2019 at 22:17, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 6/13/19 7:37 AM, Peter Maydell wrote:

> > The AArch32 VTRN instruction is specified to give an UNKNOWN

> > result if Vd and Vm are the same register; avoid generating

> > this in risu output, as we already do for VUZP and VZIP.

> >

> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> > ---

> > Alex: this pattern error is why we don't pass your

> > testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared

> > with a real Cortex-A7. You probably want to update that.

> >

> >  arm.risu | 3 ++-

> >  1 file changed, 2 insertions(+), 1 deletion(-)

>

> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


Applied to risu master, thanks.

-- PMM

Patch

diff --git a/arm.risu b/arm.risu
index 9009e6b..c16d245 100644
--- a/arm.risu
+++ b/arm.risu
@@ -613,7 +613,8 @@  VCLT0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 100 q m 0 vm:4
 VABS A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 110 q m 0 vm:4
 VNEG A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 111 q m 0 vm:4
 VSWP A1 1111 0011 1 d 11 sz:2 10 vd:4 00000 q m 0 vm:4
-VTRN A1 1111 0011 1 d 11 sz:2 10 vd:4 00001 q m 0 vm:4
+# d == m gives UNKNOWN results, so avoid it
+VTRN A1 1111 0011 1 d 11 sz:2 10 vd:4 00001 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }
 # d == m gives UNKNOWN results, so avoid it
 VUZP A1 1111 0011 1 d 11 sz:2 10 vd:4 00010 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }
 VZIP A1 1111 0011 1 d 11 sz:2 10 vd:4 00011 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }