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[209.132.180.67]) by mx.google.com with ESMTP id e8si1073936plb.420.2019.06.13.20.11.57; Thu, 13 Jun 2019 20:11:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNIF4Taq; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725834AbfFNDL5 (ORCPT + 14 others); Thu, 13 Jun 2019 23:11:57 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:42573 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfFNDL5 (ORCPT ); Thu, 13 Jun 2019 23:11:57 -0400 Received: by mail-pg1-f193.google.com with SMTP id l19so664578pgh.9 for ; Thu, 13 Jun 2019 20:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=sNIF4TaqtWZx+SWXbKFuSQaAHyH/3etk8jvo0f9cyStxOLJ7UvQrp3TwDEOw197rwO 98mN3sbimtbmJkPhi84RBjFB0UN2qrwienlr/AJgSjaPpIAWaX+3frMl5trjF+1LjlC7 k+5S98Sj+bieeo9G1hY6QVkFVZW1w6gGdz/v0owtlM8lV/YHFr9ZDCWLMyLz6Arljf+h zQc27CMZcJzoHdGRaiI2x8pU1bCcsCzzCi4eepW4MYwrdIcpbHUUBM1gMzCjZ8yFVNPi D7GLLGrHEi/XtWbRyH7DR9nFwnu6aPy2106vuNB4XahxgkFzg4j79VhVCpyfl8td3Jq4 3I6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=g8faW3pzzh6ysNe7APshV+SMr4wcjxtBa4i9CFwKyWZdE3HltGxErktOOKztoIHB69 49NblGhnP90uNHp7sNNUBkiDUDWBwR/nlfq0Q8t14hrJ4xJnlwL+QscaY8zP7ZjtdZ/D rQ74QgPQJ3EWEwvYgxPMw05p5AgTYqAutEQzOdmdSCx9JPjK4mgwHB3znRzfuyel8EKL iz1jGYK4Uigua04N/4zPnETQELSN45djH/Pm8nDVQavWvGYTz7ykHxj8MGmovzaIQOCA JoakgC+HutdxaucOlIm/pdPZn+iT1V6JTWfLaZTJNut9aUzRNR0VWMgab0RDm90euZ5M SmJQ== X-Gm-Message-State: APjAAAWbOoS3cxVhp2KCHCn41xNbub8wIPn0OkdY64UsnGOvG5lK4csW 6+EGKMAdbsW554nDJEChVZU/zg== X-Received: by 2002:a17:90a:19d:: with SMTP id 29mr8971505pjc.71.1560481916646; Thu, 13 Jun 2019 20:11:56 -0700 (PDT) Received: from localhost ([122.172.66.84]) by smtp.gmail.com with ESMTPSA id 12sm1107859pgw.55.2019.06.13.20.11.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jun 2019 20:11:56 -0700 (PDT) From: Viresh Kumar To: linux-arm-kernel@lists.infradead.org, Julien Thierry Cc: Viresh Kumar , stable@vger.kernel.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 01/45] arm64: barrier: Add CSDB macros to control data-value prediction Date: Fri, 14 Jun 2019 08:37:44 +0530 Message-Id: <9cbf3ace67c45ddb00ea1a1567d20f6954fbc15e.1560480942.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 669474e772b952b14f4de4845a1558fd4c0414a4 upstream. For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index f68abb17aa4b..683c2875278f 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -95,6 +95,13 @@ dmb \opt .endm +/* + * Value prediction barrier + */ + .macro csdb + hint #20 + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index f2d2c0bbe21b..574486634c62 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -28,6 +28,8 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define csdb() asm volatile("hint #20" : : : "memory") + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st)