From patchwork Mon Jun 17 14:33:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167044 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1091396ock; Mon, 17 Jun 2019 07:44:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqzcVJvojI1p46UTyIe2c8OTMi16rJf+YUVb50DJcfrYSzA9ETwzN662tQwCYzGhA3J9Y8c2 X-Received: by 2002:a05:6402:14d4:: with SMTP id f20mr8619258edx.125.1560782673505; Mon, 17 Jun 2019 07:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560782673; cv=none; d=google.com; s=arc-20160816; b=oRPHvtYRropFmimm0GIZx0V/QvpXWsVM0sFp3cr+FHN4EZtXDZkdc0vnttRzGFP/XW uj6xecjychLKDpgOi0rMH8GoqiSLfoOaGhXjy+vsaNZvU6QOXKvXDQKA3uIimqEot9hX FLXxp0/ReIV4eG/Vs0XHjWvQYbu09r/IazLFMYB91nS31ZiJuqT7B+ihXvAaWmdeXtq3 zfLaTr4+LMk+HkHWms0L5KzTaIMXNnbc48H1I1o9R8ane9gjp1cEESbKzQNbdZkgK2LI CaobHnZwK44iHxLY5P7ifDedI0umyxiZ0UlRJaO8ujSt5bH4sdlc2s1VZd9fLglRdlds 3GLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5wceQkO0iVo/ukmBGSUYh+JsgVf/jAUmegmqeoCkDUQ=; b=uevB7AGMbXBEJ7zXuKF0F8crPo40fkCEXV3i4E59rLRAbMe1Fc5yF65O+DJkquzh1r 3MW1eckazFyBfNKQKM2OKbSEmnYpcPo0veGSGEmK4jkhG2wBmXDs0GFgVZndRUU8jv5Q cwlLyjkAmCGL13B/nOF+0qjDsBXauk8pYDVkYMef5V9P7kICBHda8IXvmIwlY84E/+Mb gAdWn6mrNhkXfrm7qnajnRCHOUHPHnGlZD+SXaDzbxgQlZ299lKdeQ+ygOWcmCpdNTA7 moApYfQIpDemGzx5y35JvJUmARsLrsUo925mJjpHHSmYqCT14l4ToUnIqf1e15MmQSYL mRzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qjjvZMbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t16si8786176eda.244.2019.06.17.07.44.33 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Jun 2019 07:44:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qjjvZMbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48120 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcss4-0005dY-GD for patch@linaro.org; Mon, 17 Jun 2019 10:44:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46589) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hcsiF-0003Ru-UJ for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hcsiE-00080N-Jq for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:34:23 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:38767) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hcsiE-0007zH-DK for qemu-devel@nongnu.org; Mon, 17 Jun 2019 10:34:22 -0400 Received: by mail-wr1-x42f.google.com with SMTP id d18so10238557wrs.5 for ; Mon, 17 Jun 2019 07:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5wceQkO0iVo/ukmBGSUYh+JsgVf/jAUmegmqeoCkDUQ=; b=qjjvZMbCUvX0ACGwrzXIW/TdsqHYBSxy8lZS04IYFPmjVjzdSZCDnee+83klPPiewe w9OtczNdveR1qnEYi7kOrBK1cZTvt3bZpWT8ycPhqyYrklPTmGedUnjdVv1OS3Wbkyc+ WTrWzD+GA2r1+NVt2QDf7bxeJtVp6AIavk4ZTrafVeaWKm3qYsQHaTxd3JdRiVgZbr35 UZnWj3WLv1aRQmiRPl11iiFHdz2yWB6iywkco4auUrxG7j3uc8cTXnIaIHlcZbB/imUd LZhaYzioFooJj02OsQqPxQA2K4taMjvixX3wUCFB1LbD3WVS3DyBLlk9jgUBGlNR25Dt NwAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5wceQkO0iVo/ukmBGSUYh+JsgVf/jAUmegmqeoCkDUQ=; b=apZB0mpNOrjsS3jl6cgPEek+oFAswkIqDLrfn67lS5iUtCEHh8gLuhwL40litwbQUP keO6kwFjcg22REsXk3YPrfXT0jPxySO4UdAF6xHgjca0NFqALm3YYs4JMpBsKAUH8kM2 Vys9uaRLtg1ccLikUF8fMYX7cVuG5QQf9tnoCNzdDiSq4XazQJcOVnry5c8Qpn5JgaVF Y2HMfsuo6PW6O+IC4IBn3jE739QWIUXLXLvFcLnctb3be+lDIxE44vyV3JoX/S+CkLGY gtI5emfqPHz/cVSUNH/2LzNhn8KlU8yJM7EjYtsok7V551YXhAAp74ALtqZLywaDMOIM 1eIA== X-Gm-Message-State: APjAAAXcBjyb4Xz7S2ab+YfT/CG9UYIXY5kXcqZkLLOmBlQLvpRGmt5R k9Xoba+LM0b95esWwqdALNO/xI0/htvzYg== X-Received: by 2002:a5d:6212:: with SMTP id y18mr29950554wru.178.1560782061180; Mon, 17 Jun 2019 07:34:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:54 +0100 Message-Id: <20190617143412.5734-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow the DSP extension to be disabled via a CPU property for M-profile CPUs. (A and R-profile CPUs don't have this extension as a defined separate optional architecture extension, so they don't need the property.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20190517174046.11146-3-peter.maydell@linaro.org --- target/arm/cpu.h | 2 ++ target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cf2496aeeec..a98c45b1ff0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -790,6 +790,8 @@ struct ARMCPU { bool has_vfp; /* CPU has Neon */ bool has_neon; + /* CPU has M-profile DSP extension */ + bool has_dsp; /* CPU has memory protection unit */ bool has_mpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index af879d5311e..376db154f00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -769,6 +769,9 @@ static Property arm_cpu_has_vfp_property = static Property arm_cpu_has_neon_property = DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); +static Property arm_cpu_has_dsp_property = + DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); + static Property arm_cpu_has_mpu_property = DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); @@ -881,6 +884,12 @@ void arm_cpu_post_init(Object *obj) } } + if (arm_feature(&cpu->env, ARM_FEATURE_M) && + arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, + &error_abort); + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); @@ -1100,6 +1109,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.mvfr0 = u; } + if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { + uint32_t u; + + unset_feature(env, ARM_FEATURE_THUMB_DSP); + + u = cpu->isar.id_isar1; + u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); + cpu->isar.id_isar1 = u; + + u = cpu->isar.id_isar2; + u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); + u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); + cpu->isar.id_isar2 = u; + + u = cpu->isar.id_isar3; + u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); + u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); + cpu->isar.id_isar3 = u; + } + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M)) {