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[209.132.180.67]) by mx.google.com with ESMTP id 19si14516099pfi.81.2019.06.18.15.10.33; Tue, 18 Jun 2019 15:10:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=XjoG6E5A; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730692AbfFRWKd (ORCPT + 15 others); Tue, 18 Jun 2019 18:10:33 -0400 Received: from mail-qk1-f195.google.com ([209.85.222.195]:44760 "EHLO mail-qk1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729982AbfFRWKc (ORCPT ); Tue, 18 Jun 2019 18:10:32 -0400 Received: by mail-qk1-f195.google.com with SMTP id p144so9620401qke.11; Tue, 18 Jun 2019 15:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8RAVgDcgFBCOULo1eBKU4bXJqt/a804uhCnL1Ylg6ZU=; b=XjoG6E5ABG11p1wAc4l3vKqy1ahzwsGTS8GvfXWtEYROU7Vb0LV9zvVbOCM/tbW/kR whr1r9a4MkCHftg3E8umf61Ff/ZSXYlw+7Pq4sSfd4BMXalLNpr4EdhhKdmrvaNsy1nF gDAQJq3qIMpmtlNAC+/FNo9dxWbPZRPmqoe/EVaIRbyhE0Ll7xbY4TQSpfxU9q+XJakQ gc8TUNLk8iOpq/iCx8nbdEMjhP3NL3DOuYocX1W5QzPKKICBvnuqYYz17Twqwv7Hjoqf UGMVmORRcFbljojGKYfBU8gBkcv4C95JDS9G1M6lAkbM7btw8T9307XOOXl6anKUyQdG CAsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8RAVgDcgFBCOULo1eBKU4bXJqt/a804uhCnL1Ylg6ZU=; b=VQL/30KKxl2TySNYUK2WvO1HIB6qYQS9yklLMJssZ161qwZAGVStl+rcf7EFvNRouy 1/PyD0ebF8rt34qlheL8AdKcd/g9Fa7uOALdryhHcD6lnCXvbNOrOgO3s+3BJbO1szzB jKudtVhOySJBNgIqZi1MpCRDUzbgQkufmgNpnQtMUASCxFv53Hdi9q7IJLwSsLUDnmyt /HQNIW/bzHc9fcTmyA9ionaxY2KlHiBs1/a7wSupQMqRkEeVaGZiaojYvtJtMbmBIccH r55ORASDKE2nI2IyJfhdePuTZ4K3pgiqaiIQ7eKzRbJoTYee3L/znyQIQ5fGdtA+1g0l Z/iQ== X-Gm-Message-State: APjAAAW7uH3xtgdMjGjGJ3/sTk1x2rzWEAFGrw1POIsCk0XcCb4R5+Wz Xa8rdjbcnM+xDVr9gxCZxeo= X-Received: by 2002:ae9:e20c:: with SMTP id c12mr96068214qkc.210.1560895831749; Tue, 18 Jun 2019 15:10:31 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:5010:5849:d76d:b714]) by smtp.gmail.com with ESMTPSA id i123sm9480280qkd.32.2019.06.18.15.10.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 18 Jun 2019 15:10:30 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, Sean Paul , Georgi Djakov , Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Boris Brezillon , Mamta Shukla , freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5 v3] drm/msm/mdp5: Use the interconnect API Date: Tue, 18 Jun 2019 15:10:16 -0700 Message-Id: <20190618221022.28749-1-robdclark@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Georgi Djakov The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the most appropriate power/performance profile. Use the API to configure the interconnects and request bandwidth between DDR and the display hardware (MDP port(s) and rotator downscaler). v2: update the path names to be consistent with dpu, handle the NULL path case, updated commit msg from Georgi. v3: split out icc setup into it's own function, and rework logic slightly so no interconnect paths is not fatal. Signed-off-by: Georgi Djakov Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.20.1 Reviewed-By: Jeffrey Hugo diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 97179bec8902..1c55401956c4 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -16,6 +16,7 @@ * this program. If not, see . */ +#include #include #include "msm_drv.h" @@ -1048,9 +1049,46 @@ static const struct component_ops mdp5_ops = { .unbind = mdp5_unbind, }; +static int mdp5_setup_interconnect(struct platform_device *pdev) +{ + struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem"); + struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem"); + struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem"); + + if (IS_ERR(path0)) + return PTR_ERR(path0); + + if (!path0) { + /* no interconnect support is not necessarily a fatal + * condition, the platform may simply not have an + * interconnect driver yet. But warn about it in case + * bootloader didn't setup bus clocks high enough for + * scanout. + */ + dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); + return 0; + } + + icc_set_bw(path0, 0, MBps_to_icc(6400)); + + if (!IS_ERR_OR_NULL(path1)) + icc_set_bw(path1, 0, MBps_to_icc(6400)); + if (!IS_ERR_OR_NULL(path_rot)) + icc_set_bw(path_rot, 0, MBps_to_icc(6400)); + + return 0; +} + static int mdp5_dev_probe(struct platform_device *pdev) { + int ret; + DBG(""); + + ret = mdp5_setup_interconnect(pdev); + if (ret) + return ret; + return component_add(&pdev->dev, &mdp5_ops); }