From patchwork Thu Jun 20 13:06:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 167335 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2049357ilk; Thu, 20 Jun 2019 06:07:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqw/1Ek/XGCcHsdwJSVSQgmdTTMFTKivpqBwyhJN4m/L/PgPPfqe4TAVhFESVpBQf7DzazFc X-Received: by 2002:a17:90a:22ef:: with SMTP id s102mr3136497pjc.2.1561036025114; Thu, 20 Jun 2019 06:07:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561036025; cv=none; d=google.com; s=arc-20160816; b=ti9DV+8KVBTHDDJqYefI4apW76tgiBl93FMNlI2DZNXO0kUNAaqIQQfkCqu4Ko6Cev DdSWY9k7d+EKYv3wV/y27FOw02XnxemH+Eg2oASY0U5mzwHJPIcJImza4nU3ERffU2h+ JbZ+sn6qzoiUYEnziXq6llEm9urqP+Vv1YqAeRXipcpKtrTPvP1UrVxTkAIgtijGK9sk +5UKmw3xyK13NPOXSU/ymSh88NUiU3999GgQqdmEoyYPj3MhgCfCXgpovZKWggvUilWl GKqV+9XETyEpUwNIKhd/r/Me70O4/kr/oaIGvmTVYFmV3X9m/2ZSzDE9jch+O7icfrV7 ceeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=HJ7z475PfrdQrKYE9zlXfvqhCcLbgTY/s1X72OLyabo=; b=XtAHEH1nNi+3lisBuggcnIimpMkBjITwwC/jo+JZtEk651tJNq7nlfPkBQT9tS7grv YejZswIrEs7JUjd+CBi23/LqRFc3OPclMSpEiiNd+xGck9FGdBFbiWA6J/zdnasKsW4X 17O3TreWMh1aS7ZpLx0SRYa8GXOhploH9pnmai9DjpL4SKHMGYW4skNz+yjze0G2eRVv b9YjsqkZVycxQN7Mv2KfW82yOE9hdbhWmqduJo6TiMZ6Hkracv908/Tm3xcUSgdaQ67G vNDPiYvx2yMl4ZR2lmQFGytHSeCL0BUwuUEmCQ0xxAh6S3W9uXQhtXD/0/dVNRWYTffn 1POg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h8si4180374pjs.13.2019.06.20.06.07.04; Thu, 20 Jun 2019 06:07:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732107AbfFTNHD (ORCPT + 30 others); Thu, 20 Jun 2019 09:07:03 -0400 Received: from foss.arm.com ([217.140.110.172]:36800 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731983AbfFTNGh (ORCPT ); Thu, 20 Jun 2019 09:06:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 02CBFC0A; Thu, 20 Jun 2019 06:06:37 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A17143F718; Thu, 20 Jun 2019 06:06:35 -0700 (PDT) From: Julien Grall To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: james.morse@arm.com, marc.zyngier@arm.com, julien.thierry@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Grall Subject: [RFC v2 09/14] arm64/mm: Split the function check_and_switch_context in 3 parts Date: Thu, 20 Jun 2019 14:06:03 +0100 Message-Id: <20190620130608.17230-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190620130608.17230-1-julien.grall@arm.com> References: <20190620130608.17230-1-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The function check_and_switch_context is used to: 1) Check whether the ASID is still valid 2) Generate a new one if it is not valid 3) Switch the context While the latter is specific to the MM subsystem, the rest could be part of the generic ASID allocator. After this patch, the function is now split in 3 parts which corresponds to the use of the functions: 1) asid_check_context: Check if the ASID is still valid 2) asid_new_context: Generate a new ASID for the context 3) check_and_switch_context: Call 1) and 2) and switch the context 1) and 2) have not been merged in a single function because we want to avoid to add a branch in when the ASID is still valid. This will matter when the code will be moved in separate file later on as 1) will reside in the header as a static inline function. Signed-off-by: Julien Grall --- Will wants to avoid to add a branch when the ASID is still valid. So 1) and 2) are in separates function. The former will move to a new header and make static inline. --- arch/arm64/mm/context.c | 51 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 12 deletions(-) -- 2.11.0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 81bc3d365436..fbef5a5c5624 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -204,16 +204,21 @@ static u64 new_context(struct asid_info *info, atomic64_t *pasid) return idx2asid(info, asid) | generation; } -void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) +static void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu); + +/* + * Check the ASID is still valid for the context. If not generate a new ASID. + * + * @pasid: Pointer to the current ASID batch + * @cpu: current CPU ID. Must have been acquired throught get_cpu() + */ +static void asid_check_context(struct asid_info *info, + atomic64_t *pasid, unsigned int cpu) { - unsigned long flags; u64 asid, old_active_asid; - struct asid_info *info = &asid_info; - if (system_supports_cnp()) - cpu_set_reserved_ttbr0(); - - asid = atomic64_read(&mm->context.id); + asid = atomic64_read(pasid); /* * The memory ordering here is subtle. @@ -234,14 +239,30 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) !((asid ^ atomic64_read(&info->generation)) >> info->bits) && atomic64_cmpxchg_relaxed(&active_asid(info, cpu), old_active_asid, asid)) - goto switch_mm_fastpath; + return; + + asid_new_context(info, pasid, cpu); +} + +/* + * Generate a new ASID for the context. + * + * @pasid: Pointer to the current ASID batch allocated. It will be updated + * with the new ASID batch. + * @cpu: current CPU ID. Must have been acquired through get_cpu() + */ +static void asid_new_context(struct asid_info *info, atomic64_t *pasid, + unsigned int cpu) +{ + unsigned long flags; + u64 asid; raw_spin_lock_irqsave(&info->lock, flags); /* Check that our ASID belongs to the current generation. */ - asid = atomic64_read(&mm->context.id); + asid = atomic64_read(pasid); if ((asid ^ atomic64_read(&info->generation)) >> info->bits) { - asid = new_context(info, &mm->context.id); - atomic64_set(&mm->context.id, asid); + asid = new_context(info, pasid); + atomic64_set(pasid, asid); } if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) @@ -249,8 +270,14 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) atomic64_set(&active_asid(info, cpu), asid); raw_spin_unlock_irqrestore(&info->lock, flags); +} + +void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) +{ + if (system_supports_cnp()) + cpu_set_reserved_ttbr0(); -switch_mm_fastpath: + asid_check_context(&asid_info, &mm->context.id, cpu); arm64_apply_bp_hardening();